RE: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation processors

[Babu Moger]

Hi Pankaj,

> -----Original Message-----
> From: Pankaj Gupta <pankaj.gupta.linux@gmail.com>
> Sent: Wednesday, February 24, 2021 2:19 AM
> To: Moger, Babu <Babu.Moger@amd.com>
> Cc: Paolo Bonzini <pbonzini@redhat.com>; richard.henderson@linaro.org;
> Eduardo Habkost <ehabkost@redhat.com>; Qemu Developers <qemu-
> devel@nongnu.org>
> Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation
> processors
> 
> Hi Babu,
> 
> > >> +        .features[FEAT_8000_0008_EBX] =
> > >> +            CPUID_8000_0008_EBX_CLZERO |
> CPUID_8000_0008_EBX_XSAVEERPTR |
> > >> +            CPUID_8000_0008_EBX_WBNOINVD |
> CPUID_8000_0008_EBX_IBPB |
> > >> +            CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
> > >> +            CPUID_8000_0008_EBX_AMD_SSBD,
> > >
> > > Don't have SSBD flag exposed in default EPYC-Rome CPU configuration?
> > > Is there any reason for this?
> > > Or do we need to explicitly add it?
> >
> > I think we missed it when we added EPYC-Rome model. I was going to add
> > it sometime soon. As you know users can still add it with "+ssbd" if 
> > required.
> 
> Thanks for clarifying. I also see CPUID_8000_0008_EBX_IBRS missing for Rome.
> Will it be okay if we add them now for Rome?

It is normally added as v2 for compatibility. Like this.

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 24db7ed892..f721d0db78 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4179,6 +4179,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
         .xlevel = 0x8000001E,
         .model_id = "AMD EPYC-Rome Processor",
         .cache_info = &epyc_rome_cache_info,
+        .versions = (X86CPUVersionDefinition[]) {
+            { .version = 1 },
+            {
+                .version = 2,
+                .props = (PropValue[]) {
+                    { "ibrs", "on" },
+                    { "amd-ssbd", "on" },
+                    { "model-id",
+                      "AMD EPYC-Rome Processor" },
+                    { /* end of list */ }
+                }
+            },
+            { /* end of list */ }
+        }
     },
     {
         .name = "EPYC-Milan",
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c index
> 6a53446e6a..b495116545 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -4161,7 +4161,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
>          .features[FEAT_8000_0008_EBX] =
>              CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR
> |
>              CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
> -            CPUID_8000_0008_EBX_STIBP,
> +            CPUID_8000_0008_EBX_STIBP | CPUID_8000_0008_EBX_IBRS |
> +            CPUID_8000_0008_EBX_AMD_SSBD,
>          .features[FEAT_7_0_EBX] =
>              CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
> CPUID_7_0_EBX_AVX2 |
>              CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
> CPUID_7_0_EBX_RDSEED |