[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v1 1/3] target/ppc: Fix POWER9 radix guest HV interrupt AIL b
From: |
Fabiano Rosas |
Subject: |
Re: [PATCH v1 1/3] target/ppc: Fix POWER9 radix guest HV interrupt AIL behaviour |
Date: |
Tue, 13 Apr 2021 10:48:56 -0300 |
Nicholas Piggin <npiggin@gmail.com> writes:
> ISA v3.0 radix guest execution has a quirk in AIL behaviour such that
> the LPCR[AIL] value can apply to hypervisor interrupts.
>
> This affects machines that emulate HV=1 mode (i.e., powernv9).
>
Ah ok, so we actually want to replicate the quirk in the pnv
machine. Took me a while.
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> target/ppc/excp_helper.c | 17 +++++++++++++----
> 1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 85de7e6c90..b8881c0f85 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -791,14 +791,23 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> #endif
>
> /*
> - * AIL only works if there is no HV transition and we are running
> - * with translations enabled
> + * AIL only works if MSR[IR] and MSR[DR] are both enabled.
> */
> - if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) ||
> - ((new_msr & MSR_HVB) && !(msr & MSR_HVB))) {
> + if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1)) {
> ail = 0;
> }
>
> + /*
> + * AIL does not work if there is a MSR[HV] 0->1 transition and the
> + * partition is in HPT mode. For radix guests, such interrupts are
> + * allowed to be delivered to the hypervisor in ail mode.
> + */
> + if ((new_msr & MSR_HVB) && !(msr & MSR_HVB)) {
> + if (!(env->spr[SPR_LPCR] & LPCR_HR)) {
> + ail = 0;
> + }
> + }
> +
> vector = env->excp_vectors[excp];
> if (vector == (target_ulong)-1ULL) {
> cpu_abort(cs, "Raised an exception without defined vector %d\n",