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[PULL 00/32] riscv-to-apply queue
From: |
Alistair Francis |
Subject: |
[PULL 00/32] riscv-to-apply queue |
Date: |
Tue, 8 Jun 2021 10:29:15 +1000 |
The following changes since commit a35947f15c0ee695eba3c55248ec8ac3e4e23cca:
Merge remote-tracking branch
'remotes/stsquad/tags/pull-testing-updates-070621-2' into staging (2021-06-07
15:45:48 +0100)
are available in the Git repository at:
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210608-1
for you to fetch changes up to d2c1a177b138be35cb96216baa870c3564b123e4:
target/riscv: rvb: add b-ext version cpu option (2021-06-08 09:59:46 +1000)
----------------------------------------------------------------
Second RISC-V PR for QEMU 6.1
- Update the PLIC and CLINT DT bindings
- Improve documentation for RISC-V machines
- Support direct kernel boot for microchip_pfsoc
- Fix WFI exception behaviour
- Improve CSR printing
- Initial support for the experimental Bit Manip extension
----------------------------------------------------------------
Alistair Francis (2):
docs/system: Move the RISC-V -bios information to removed
target/riscv/pmp: Add assert for ePMP operations
Bin Meng (9):
hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper
hw/riscv: Support the official CLINT DT bindings
hw/riscv: Support the official PLIC DT bindings
docs/system/riscv: Correct the indentation level of supported devices
docs/system/riscv: sifive_u: Document '-dtb' usage
hw/riscv: Use macros for BIOS image names
hw/riscv: microchip_pfsoc: Support direct kernel boot
target/riscv: Remove unnecessary riscv_*_names[] declaration
Changbin Du (1):
target/riscv: Dump CSR mscratch/sscratch/satp
Frank Chang (6):
target/riscv: rvb: count bits set
target/riscv: add gen_shifti() and gen_shiftiw() helper functions
target/riscv: rvb: single-bit instructions
target/riscv: rvb: generalized reverse
target/riscv: rvb: generalized or-combine
target/riscv: rvb: add b-ext version cpu option
Jose Martins (1):
target/riscv: fix wfi exception behavior
Kito Cheng (11):
target/riscv: reformat @sh format encoding for B-extension
target/riscv: rvb: count leading/trailing zeros
target/riscv: rvb: logic-with-negate
target/riscv: rvb: pack two words into one register
target/riscv: rvb: min/max instructions
target/riscv: rvb: sign-extend instructions
target/riscv: rvb: shift ones
target/riscv: rvb: rotate (left/right)
target/riscv: rvb: address calculation
target/riscv: rvb: add/shift with prefix zero-extend
target/riscv: rvb: support and turn on B-extension from command line
LIU Zhiwei (1):
target/riscv: Pass the same value to oprsz and maxsz.
Philippe Mathieu-Daudé (1):
target/riscv: Do not include 'pmp.h' in user emulation
docs/system/deprecated.rst | 19 --
docs/system/removed-features.rst | 5 +
docs/system/riscv/microchip-icicle-kit.rst | 50 +++-
docs/system/riscv/sifive_u.rst | 77 +++--
docs/system/target-riscv.rst | 13 +-
include/hw/riscv/boot.h | 5 +
target/riscv/cpu.h | 9 +-
target/riscv/cpu_bits.h | 1 +
target/riscv/helper.h | 6 +
target/riscv/insn32.decode | 87 +++++-
hw/riscv/microchip_pfsoc.c | 81 +++++-
hw/riscv/sifive_u.c | 24 +-
hw/riscv/spike.c | 12 +-
hw/riscv/virt.c | 25 +-
target/riscv/bitmanip_helper.c | 90 ++++++
target/riscv/cpu.c | 38 ++-
target/riscv/op_helper.c | 11 +-
target/riscv/pmp.c | 4 +
target/riscv/translate.c | 306 ++++++++++++++++++++
target/riscv/insn_trans/trans_rvb.c.inc | 438 +++++++++++++++++++++++++++++
target/riscv/insn_trans/trans_rvi.c.inc | 54 +---
target/riscv/insn_trans/trans_rvv.c.inc | 89 +++---
target/riscv/meson.build | 1 +
23 files changed, 1260 insertions(+), 185 deletions(-)
create mode 100644 target/riscv/bitmanip_helper.c
create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
- [PULL 00/32] riscv-to-apply queue,
Alistair Francis <=
- [PULL 01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper, Alistair Francis, 2021/06/07
- [PULL 02/32] hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper, Alistair Francis, 2021/06/07
- [PULL 03/32] hw/riscv: Support the official CLINT DT bindings, Alistair Francis, 2021/06/07
- [PULL 04/32] hw/riscv: Support the official PLIC DT bindings, Alistair Francis, 2021/06/07
- [PULL 05/32] docs/system/riscv: Correct the indentation level of supported devices, Alistair Francis, 2021/06/07
- [PULL 06/32] docs/system/riscv: sifive_u: Document '-dtb' usage, Alistair Francis, 2021/06/07
- [PULL 07/32] hw/riscv: Use macros for BIOS image names, Alistair Francis, 2021/06/07
- [PULL 08/32] hw/riscv: microchip_pfsoc: Support direct kernel boot, Alistair Francis, 2021/06/07
- [PULL 09/32] target/riscv: fix wfi exception behavior, Alistair Francis, 2021/06/07
- [PULL 10/32] docs/system: Move the RISC-V -bios information to removed, Alistair Francis, 2021/06/07