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[PULL 04/32] hw/riscv: Support the official PLIC DT bindings
From: |
Alistair Francis |
Subject: |
[PULL 04/32] hw/riscv: Support the official PLIC DT bindings |
Date: |
Tue, 8 Jun 2021 10:29:19 +1000 |
From: Bin Meng <bin.meng@windriver.com>
The official DT bindings of PLIC uses "sifive,plic-1.0.0" as the
compatible string in the upstream Linux kernel. "riscv,plic0" is
now legacy and has to be kept for backward compatibility of legacy
systems.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-4-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 6 +++++-
hw/riscv/virt.c | 6 +++++-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index d3828dc880..a32a95d58f 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -101,6 +101,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry
*memmap,
static const char * const clint_compat[2] = {
"sifive,clint0", "riscv,clint0"
};
+ static const char * const plic_compat[2] = {
+ "sifive,plic-1.0.0", "riscv,plic0"
+ };
if (ms->dtb) {
fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
@@ -270,7 +273,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry
*memmap,
(long)memmap[SIFIVE_U_DEV_PLIC].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
- qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
+ qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
+ (char **)&plic_compat, ARRAY_SIZE(plic_compat));
qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 5159e7e020..560216d217 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -197,6 +197,9 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry
*memmap,
static const char * const clint_compat[2] = {
"sifive,clint0", "riscv,clint0"
};
+ static const char * const plic_compat[2] = {
+ "sifive,plic-1.0.0", "riscv,plic0"
+ };
if (mc->dtb) {
fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
@@ -319,7 +322,8 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry
*memmap,
"#address-cells", FDT_PLIC_ADDR_CELLS);
qemu_fdt_setprop_cell(fdt, plic_name,
"#interrupt-cells", FDT_PLIC_INT_CELLS);
- qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0");
+ qemu_fdt_setprop_string_array(fdt, plic_name, "compatible",
+ (char **)&plic_compat, ARRAY_SIZE(plic_compat));
qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
--
2.31.1
- [PULL 00/32] riscv-to-apply queue, Alistair Francis, 2021/06/07
- [PULL 01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper, Alistair Francis, 2021/06/07
- [PULL 02/32] hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper, Alistair Francis, 2021/06/07
- [PULL 03/32] hw/riscv: Support the official CLINT DT bindings, Alistair Francis, 2021/06/07
- [PULL 04/32] hw/riscv: Support the official PLIC DT bindings,
Alistair Francis <=
- [PULL 05/32] docs/system/riscv: Correct the indentation level of supported devices, Alistair Francis, 2021/06/07
- [PULL 06/32] docs/system/riscv: sifive_u: Document '-dtb' usage, Alistair Francis, 2021/06/07
- [PULL 07/32] hw/riscv: Use macros for BIOS image names, Alistair Francis, 2021/06/07
- [PULL 08/32] hw/riscv: microchip_pfsoc: Support direct kernel boot, Alistair Francis, 2021/06/07
- [PULL 09/32] target/riscv: fix wfi exception behavior, Alistair Francis, 2021/06/07
- [PULL 10/32] docs/system: Move the RISC-V -bios information to removed, Alistair Francis, 2021/06/07
- [PULL 11/32] target/riscv: Do not include 'pmp.h' in user emulation, Alistair Francis, 2021/06/07
- [PULL 12/32] target/riscv: Remove unnecessary riscv_*_names[] declaration, Alistair Francis, 2021/06/07
- [PULL 13/32] target/riscv: Dump CSR mscratch/sscratch/satp, Alistair Francis, 2021/06/07
- [PULL 14/32] target/riscv/pmp: Add assert for ePMP operations, Alistair Francis, 2021/06/07