[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 19/37] s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED
From: |
Cornelia Huck |
Subject: |
[PULL 19/37] s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED |
Date: |
Mon, 21 Jun 2021 11:58:24 +0200 |
From: David Hildenbrand <david@redhat.com>
128 bit -> 64 bit, there is only a single element to process.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-19-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/s390x/helper.h | 1 +
target/s390x/translate_vx.c.inc | 11 ++++++++++-
target/s390x/vec_fpu_helper.c | 19 +++++++++++++++++++
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index b5ba159402b2..02e6967ae6b5 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -287,6 +287,7 @@ DEF_HELPER_FLAGS_4(gvec_vfi128, TCG_CALL_NO_WG, void, ptr,
cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfll32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfll64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vflr64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vflr128, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfm32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfm64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfm128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env,
i32)
diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc
index 472afca45e25..e94c9f9d86d5 100644
--- a/target/s390x/translate_vx.c.inc
+++ b/target/s390x/translate_vx.c.inc
@@ -2759,8 +2759,17 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps
*o)
}
break;
case 0xc5:
- if (fpf == FPF_LONG) {
+ switch (fpf) {
+ case FPF_LONG:
fn = gen_helper_gvec_vflr64;
+ break;
+ case FPF_EXT:
+ if (s390_has_feat(S390_FEAT_VECTOR_ENH)) {
+ fn = gen_helper_gvec_vflr128;
+ }
+ break;
+ default:
+ break;
}
break;
default:
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index 75e3212582bc..0fb82bd18f46 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -563,6 +563,25 @@ void HELPER(gvec_vflr64)(void *v1, const void *v2,
CPUS390XState *env,
*(S390Vector *)v1 = tmp;
}
+void HELPER(gvec_vflr128)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ const uint8_t erm = extract32(simd_data(desc), 4, 4);
+ const bool XxC = extract32(simd_data(desc), 2, 1);
+ uint8_t vxc, vec_exc = 0;
+ int old_mode;
+ float64 ret;
+
+ old_mode = s390_swap_bfp_rounding_mode(env, erm);
+ ret = float128_to_float64(s390_vec_read_float128(v2), &env->fpu_status);
+ vxc = check_ieee_exc(env, 0, XxC, &vec_exc);
+ s390_restore_bfp_rounding_mode(env, old_mode);
+ handle_ieee_exc(env, vxc, vec_exc, GETPC());
+
+ /* place at even element, odd element is unpredictable */
+ s390_vec_write_float64(v1, 0, ret);
+}
+
static void vfma64(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
const S390Vector *v4, CPUS390XState *env, bool s, int flags,
uintptr_t retaddr)
--
2.31.1
- [PULL 10/37] s390x/tcg: Simplify vflr64() handling, (continued)
- [PULL 10/37] s390x/tcg: Simplify vflr64() handling, Cornelia Huck, 2021/06/21
- [PULL 09/37] s390x/tcg: Simplify vfll32() handling, Cornelia Huck, 2021/06/21
- [PULL 11/37] s390x/tcg: Simplify wfc64() handling, Cornelia Huck, 2021/06/21
- [PULL 12/37] s390x/tcg: Implement VECTOR BIT PERMUTE, Cornelia Huck, 2021/06/21
- [PULL 14/37] s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT), Cornelia Huck, 2021/06/21
- [PULL 13/37] s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICAL, Cornelia Huck, 2021/06/21
- [PULL 15/37] s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT), Cornelia Huck, 2021/06/21
- [PULL 16/37] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE *, Cornelia Huck, 2021/06/21
- [PULL 18/37] s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED, Cornelia Huck, 2021/06/21
- [PULL 17/37] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALAR, Cornelia Huck, 2021/06/21
- [PULL 19/37] s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED,
Cornelia Huck <=
- [PULL 21/37] s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATE, Cornelia Huck, 2021/06/21
- [PULL 20/37] s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATION, Cornelia Huck, 2021/06/21
- [PULL 23/37] s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT), Cornelia Huck, 2021/06/21
- [PULL 24/37] s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM), Cornelia Huck, 2021/06/21
- [PULL 22/37] s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT), Cornelia Huck, 2021/06/21
- [PULL 25/37] linux-user: elf: s390x: Prepare for Vector enhancements facility, Cornelia Huck, 2021/06/21
- [PULL 27/37] s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z14 GA2, Cornelia Huck, 2021/06/21
- [PULL 26/37] s390x/tcg: We support Vector enhancements facility, Cornelia Huck, 2021/06/21
- [PULL 28/37] configure: Check whether we can compile the s390-ccw bios with -msoft-float, Cornelia Huck, 2021/06/21
- [PULL 29/37] target/s390x: Expose load_psw and get_psw_mask to cpu.h, Cornelia Huck, 2021/06/21