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[PULL 28/57] target/arm: Implement MVE VHADD, VHSUB
From: |
Peter Maydell |
Subject: |
[PULL 28/57] target/arm: Implement MVE VHADD, VHSUB |
Date: |
Mon, 21 Jun 2021 17:28:04 +0100 |
Implement MVE VHADD and VHSUB insns, which perform an addition
or subtraction and then halve the result.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-18-peter.maydell@linaro.org
---
target/arm/helper-mve.h | 14 ++++++++++++++
target/arm/mve.decode | 5 +++++
target/arm/mve_helper.c | 25 +++++++++++++++++++++++++
target/arm/translate-mve.c | 4 ++++
4 files changed, 48 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 5cd4e7d736d..02bef53ed41 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -116,3 +116,17 @@ DEF_HELPER_FLAGS_4(mve_vabdsw, TCG_CALL_NO_WG, void, env,
ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vabdub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vabduh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vabduw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vhaddsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vhaddsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vhaddsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vhaddub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vhadduh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vhadduw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vhsubsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vhsubsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vhsubsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vhsubub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vhsubuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vhsubuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 087d3db2a31..241d1c44c19 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -96,6 +96,11 @@ VMIN_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 1
... 0 @2op
VABD_S 111 0 1111 0 . .. ... 0 ... 0 0111 . 1 . 0 ... 0 @2op
VABD_U 111 1 1111 0 . .. ... 0 ... 0 0111 . 1 . 0 ... 0 @2op
+VHADD_S 111 0 1111 0 . .. ... 0 ... 0 0000 . 1 . 0 ... 0 @2op
+VHADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 0 ... 0 @2op
+VHSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op
+VHSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op
+
# Vector miscellaneous
VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 63eacd7349b..835832fdf69 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -429,3 +429,28 @@ DO_2OP_U(vminu, DO_MIN)
DO_2OP_S(vabds, DO_ABD)
DO_2OP_U(vabdu, DO_ABD)
+
+static inline uint32_t do_vhadd_u(uint32_t n, uint32_t m)
+{
+ return ((uint64_t)n + m) >> 1;
+}
+
+static inline int32_t do_vhadd_s(int32_t n, int32_t m)
+{
+ return ((int64_t)n + m) >> 1;
+}
+
+static inline uint32_t do_vhsub_u(uint32_t n, uint32_t m)
+{
+ return ((uint64_t)n - m) >> 1;
+}
+
+static inline int32_t do_vhsub_s(int32_t n, int32_t m)
+{
+ return ((int64_t)n - m) >> 1;
+}
+
+DO_2OP_S(vhadds, do_vhadd_s)
+DO_2OP_U(vhaddu, do_vhadd_u)
+DO_2OP_S(vhsubs, do_vhsub_s)
+DO_2OP_U(vhsubu, do_vhsub_u)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 041fd1ef14f..f593d3693b9 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -357,3 +357,7 @@ DO_2OP(VMIN_S, vmins)
DO_2OP(VMIN_U, vminu)
DO_2OP(VABD_S, vabds)
DO_2OP(VABD_U, vabdu)
+DO_2OP(VHADD_S, vhadds)
+DO_2OP(VHADD_U, vhaddu)
+DO_2OP(VHSUB_S, vhsubs)
+DO_2OP(VHSUB_U, vhsubu)
--
2.20.1
- [PULL 37/57] target/arm: Implement MVE VPST, (continued)
- [PULL 37/57] target/arm: Implement MVE VPST, Peter Maydell, 2021/06/21
- [PULL 38/57] target/arm: Implement MVE VQADD and VQSUB, Peter Maydell, 2021/06/21
- [PULL 34/57] target/arm: Implement MVE VSUB, VMUL (scalar), Peter Maydell, 2021/06/21
- [PULL 42/57] target/arm: Implement MVE VQADD, VQSUB (vector), Peter Maydell, 2021/06/21
- [PULL 24/57] target/arm: Implement MVE VMULH, Peter Maydell, 2021/06/21
- [PULL 14/57] target/arm: Implement MVE VCLZ, Peter Maydell, 2021/06/21
- [PULL 13/57] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns, Peter Maydell, 2021/06/21
- [PULL 18/57] target/arm: Implement MVE VABS, Peter Maydell, 2021/06/21
- [PULL 22/57] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR, Peter Maydell, 2021/06/21
- [PULL 27/57] target/arm: Implement MVE VABD, Peter Maydell, 2021/06/21
- [PULL 28/57] target/arm: Implement MVE VHADD, VHSUB,
Peter Maydell <=
- [PULL 29/57] target/arm: Implement MVE VMULL, Peter Maydell, 2021/06/21
- [PULL 32/57] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH, Peter Maydell, 2021/06/21
- [PULL 33/57] target/arm: Implement MVE VADD (scalar), Peter Maydell, 2021/06/21
- [PULL 31/57] target/arm: Implement MVE VMLSLDAV, Peter Maydell, 2021/06/21
- [PULL 35/57] target/arm: Implement MVE VHADD, VHSUB (scalar), Peter Maydell, 2021/06/21
- [PULL 40/57] target/arm: Implement MVE VQDMULL scalar, Peter Maydell, 2021/06/21
- [PULL 36/57] target/arm: Implement MVE VBRSR, Peter Maydell, 2021/06/21
- [PULL 43/57] target/arm: Implement MVE VQSHL (vector), Peter Maydell, 2021/06/21
- [PULL 45/57] target/arm: Implement MVE VSHL insn, Peter Maydell, 2021/06/21
- [PULL 46/57] target/arm: Implement MVE VRSHL, Peter Maydell, 2021/06/21