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[PATCH v4 12/16] tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec
From: |
Richard Henderson |
Subject: |
[PATCH v4 12/16] tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec |
Date: |
Fri, 25 Jun 2021 22:03:03 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target.h | 2 +-
tcg/s390x/tcg-target.c.inc | 25 +++++++++++++++++++++++++
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index 8dce6af5af..275f980cee 100644
--- a/tcg/s390x/tcg-target.h
+++ b/tcg/s390x/tcg-target.h
@@ -156,7 +156,7 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_shv_vec 1
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 0
-#define TCG_TARGET_HAS_minmax_vec 0
+#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 0
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index b9d12e579b..b96128760f 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -282,6 +282,10 @@ typedef enum S390Opcode {
VRRc_VESRAV = 0xe77a,
VRRc_VESRLV = 0xe778,
VRRc_VML = 0xe7a2,
+ VRRc_VMN = 0xe7fe,
+ VRRc_VMNL = 0xe7fc,
+ VRRc_VMX = 0xe7ff,
+ VRRc_VMXL = 0xe7fd,
VRRc_VN = 0xe768,
VRRc_VNC = 0xe769,
VRRc_VNO = 0xe76b,
@@ -2735,6 +2739,19 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece);
break;
+ case INDEX_op_smin_vec:
+ tcg_out_insn(s, VRRc, VMN, a0, a1, a2, vece);
+ break;
+ case INDEX_op_smax_vec:
+ tcg_out_insn(s, VRRc, VMX, a0, a1, a2, vece);
+ break;
+ case INDEX_op_umin_vec:
+ tcg_out_insn(s, VRRc, VMNL, a0, a1, a2, vece);
+ break;
+ case INDEX_op_umax_vec:
+ tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece);
+ break;
+
case INDEX_op_cmp_vec:
switch ((TCGCond)args[3]) {
case TCG_COND_EQ:
@@ -2781,7 +2798,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_shri_vec:
case INDEX_op_shrs_vec:
case INDEX_op_shrv_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_smin_vec:
case INDEX_op_sub_vec:
+ case INDEX_op_umax_vec:
+ case INDEX_op_umin_vec:
case INDEX_op_xor_vec:
return 1;
case INDEX_op_cmp_vec:
@@ -3042,6 +3063,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_smin_vec:
+ case INDEX_op_umax_vec:
+ case INDEX_op_umin_vec:
return C_O1_I2(v, v, v);
case INDEX_op_rotls_vec:
case INDEX_op_shls_vec:
--
2.25.1
- [PATCH v4 03/16] tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg, (continued)
- [PATCH v4 03/16] tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg, Richard Henderson, 2021/06/26
- [PATCH v4 06/16] tcg/s390x: Implement tcg_out_mov for vector types, Richard Henderson, 2021/06/26
- [PATCH v4 05/16] tcg/s390x: Implement tcg_out_ld/st for vector types, Richard Henderson, 2021/06/26
- [PATCH v4 04/16] tcg/s390x: Add host vector framework, Richard Henderson, 2021/06/26
- [PATCH v4 07/16] tcg/s390x: Implement tcg_out_dup*_vec, Richard Henderson, 2021/06/26
- [PATCH v4 10/16] tcg/s390x: Implement TCG_TARGET_HAS_mul_vec, Richard Henderson, 2021/06/26
- [PATCH v4 08/16] tcg/s390x: Implement minimal vector operations, Richard Henderson, 2021/06/26
- [PATCH v4 11/16] tcg/s390x: Implement vector shift operations, Richard Henderson, 2021/06/26
- [PATCH v4 09/16] tcg/s390x: Implement andc, orc, abs, neg, not vector operations, Richard Henderson, 2021/06/26
- [PATCH v4 15/16] tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec, Richard Henderson, 2021/06/26
- [PATCH v4 12/16] tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec,
Richard Henderson <=
- [PATCH v4 13/16] tcg: Expand usadd/ussub with umin/umax, Richard Henderson, 2021/06/26
- [PATCH v4 14/16] tcg/s390x: Implement TCG_TARGET_HAS_sat_vec, Richard Henderson, 2021/06/26
- [PATCH v4 16/16] tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec, Richard Henderson, 2021/06/26
- Re: [PATCH v4 00/16] tcg/s390x: host vector support, no-reply, 2021/06/26