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[PATCH 12/17] target/riscv: Use gpr_{src,dst} for RVF
From: |
Richard Henderson |
Subject: |
[PATCH 12/17] target/riscv: Use gpr_{src,dst} for RVF |
Date: |
Thu, 8 Jul 2021 21:26:03 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvf.c.inc | 131 +++++++++---------------
1 file changed, 49 insertions(+), 82 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc
b/target/riscv/insn_trans/trans_rvf.c.inc
index 89f78701e7..ff8e942199 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -27,14 +27,23 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
- tcg_gen_addi_tl(t0, t0, a->imm);
- tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
- gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
+ TCGv addr = gpr_src(ctx, a->rs1);
+ TCGv temp = NULL;
- tcg_temp_free(t0);
+ if (a->imm) {
+ temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, addr, a->imm);
+ addr = temp;
+ }
+
+ TCGv_i64 dest = cpu_fpr[a->rd];
+ tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
+ gen_nanbox_s(dest, dest);
+
+ if (temp) {
+ tcg_temp_free(temp);
+ }
mark_fs_dirty(ctx);
return true;
}
@@ -43,14 +52,21 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
- tcg_gen_addi_tl(t0, t0, a->imm);
+ TCGv addr = gpr_src(ctx, a->rs1);
+ TCGv temp = NULL;
- tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
+ if (a->imm) {
+ temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, addr, a->imm);
+ addr = temp;
+ }
- tcg_temp_free(t0);
+ tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
+
+ if (temp) {
+ tcg_temp_free(temp);
+ }
return true;
}
@@ -271,12 +287,8 @@ static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s
*a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
-
+ gen_helper_fcvt_w_s(gpr_dst(ctx, a->rd), cpu_env, cpu_fpr[a->rs1]);
return true;
}
@@ -285,12 +297,8 @@ static bool trans_fcvt_wu_s(DisasContext *ctx,
arg_fcvt_wu_s *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
-
+ gen_helper_fcvt_wu_s(gpr_dst(ctx, a->rd), cpu_env, cpu_fpr[a->rs1]);
return true;
}
@@ -300,17 +308,14 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w
*a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
+ TCGv dest = gpr_dst(ctx, a->rd);
#if defined(TARGET_RISCV64)
- tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
+ tcg_gen_ext32s_tl(dest, cpu_fpr[a->rs1]);
#else
- tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
+ tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]);
#endif
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
-
return true;
}
@@ -318,10 +323,9 @@ static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
- gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
+
+ gen_helper_feq_s(gpr_dst(ctx, a->rd), cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
return true;
}
@@ -329,10 +333,9 @@ static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
- gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
+
+ gen_helper_flt_s(gpr_dst(ctx, a->rd), cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
return true;
}
@@ -340,10 +343,9 @@ static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
{
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
- gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
+
+ gen_helper_fle_s(gpr_dst(ctx, a->rd), cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
return true;
}
@@ -352,13 +354,7 @@ static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s
*a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
-
- gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
-
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
-
+ gen_helper_fclass_s(gpr_dst(ctx, a->rd), cpu_fpr[a->rs1]);
return true;
}
@@ -367,15 +363,10 @@ static bool trans_fcvt_s_w(DisasContext *ctx,
arg_fcvt_s_w *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
-
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
+ gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, gpr_src(ctx, a->rs1));
mark_fs_dirty(ctx);
- tcg_temp_free(t0);
-
return true;
}
@@ -384,15 +375,10 @@ static bool trans_fcvt_s_wu(DisasContext *ctx,
arg_fcvt_s_wu *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
-
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
+ gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, gpr_src(ctx, a->rs1));
mark_fs_dirty(ctx);
- tcg_temp_free(t0);
-
return true;
}
@@ -402,15 +388,10 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x
*a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
-
- tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0);
+ tcg_gen_extu_tl_i64(cpu_fpr[a->rd], gpr_src(ctx, a->rs1));
gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
mark_fs_dirty(ctx);
- tcg_temp_free(t0);
-
return true;
}
@@ -420,11 +401,8 @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s
*a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
+ gen_helper_fcvt_l_s(gpr_dst(ctx, a->rd), cpu_env, cpu_fpr[a->rs1]);
return true;
}
@@ -434,11 +412,8 @@ static bool trans_fcvt_lu_s(DisasContext *ctx,
arg_fcvt_lu_s *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
- gen_set_gpr(a->rd, t0);
- tcg_temp_free(t0);
+ gen_helper_fcvt_lu_s(gpr_dst(ctx, a->rd), cpu_env, cpu_fpr[a->rs1]);
return true;
}
@@ -448,14 +423,10 @@ static bool trans_fcvt_s_l(DisasContext *ctx,
arg_fcvt_s_l *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
-
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
+ gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, gpr_src(ctx, a->rs1));
mark_fs_dirty(ctx);
- tcg_temp_free(t0);
return true;
}
@@ -465,13 +436,9 @@ static bool trans_fcvt_s_lu(DisasContext *ctx,
arg_fcvt_s_lu *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
-
gen_set_rm(ctx, a->rm);
- gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
+ gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, gpr_src(ctx, a->rs1));
mark_fs_dirty(ctx);
- tcg_temp_free(t0);
return true;
}
--
2.25.1
- Re: [PATCH 06/17] target/riscv: Use gpr_src in branches, (continued)
- [PATCH 16/17] target/riscv: Use gpr_{src,dst} for RVV, Richard Henderson, 2021/07/09
- [PATCH 07/17] target/riscv: Use gpr_{src,dst} for integer load/store, Richard Henderson, 2021/07/09
- [PATCH 08/17] target/riscv: Use gpr_{src, dst} for word shift operations, Richard Henderson, 2021/07/09
- [PATCH 09/17] target/riscv: Reorg csr instructions, Richard Henderson, 2021/07/09
- [PATCH 11/17] target/riscv: Use gpr_{src,dst} for RVB, Richard Henderson, 2021/07/09
- [PATCH 12/17] target/riscv: Use gpr_{src,dst} for RVF,
Richard Henderson <=
- [PATCH 13/17] target/riscv: Use gpr_{src,dst} for RVD, Richard Henderson, 2021/07/09
- [PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu, Richard Henderson, 2021/07/09
- [PATCH 17/17] target/riscv: Remove gen_get_gpr, Richard Henderson, 2021/07/09
- Re: [PATCH 00/17] target/riscv: Use tcg_constant_*, LIU Zhiwei, 2021/07/15