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[PULL 03/11] docs/system: riscv: Fix CLINT name in the sifive_u doc
From: |
Alistair Francis |
Subject: |
[PULL 03/11] docs/system: riscv: Fix CLINT name in the sifive_u doc |
Date: |
Mon, 12 Jul 2021 15:53:40 -0700 |
From: Bin Meng <bmeng.cn@gmail.com>
It's Core *Local* Interruptor, not 'Level'.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627142816.19789-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/riscv/sifive_u.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst
index 32d0a1b85d..01108b5ecc 100644
--- a/docs/system/riscv/sifive_u.rst
+++ b/docs/system/riscv/sifive_u.rst
@@ -11,7 +11,7 @@ The ``sifive_u`` machine supports the following devices:
* 1 E51 / E31 core
* Up to 4 U54 / U34 cores
-* Core Level Interruptor (CLINT)
+* Core Local Interruptor (CLINT)
* Platform-Level Interrupt Controller (PLIC)
* Power, Reset, Clock, Interrupt (PRCI)
* L2 Loosely Integrated Memory (L2-LIM)
--
2.31.1
- [PULL 00/11] riscv-to-apply queue, Alistair Francis, 2021/07/12
- [PULL 01/11] target/riscv: pmp: Fix some typos, Alistair Francis, 2021/07/12
- [PULL 07/11] hw/riscv: sifive_u: Correct the CLINT timebase frequency, Alistair Francis, 2021/07/12
- [PULL 03/11] docs/system: riscv: Fix CLINT name in the sifive_u doc,
Alistair Francis <=
- [PULL 02/11] target/riscv: csr: Remove redundant check in fp csr read/write routines, Alistair Francis, 2021/07/12
- [PULL 08/11] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned, Alistair Francis, 2021/07/12
- [PULL 04/11] docs/system: riscv: Add documentation for virt machine, Alistair Francis, 2021/07/12
- [PULL 09/11] char: ibex_uart: Update the register layout, Alistair Francis, 2021/07/12
- [PULL 06/11] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot, Alistair Francis, 2021/07/12
- [PULL 05/11] target/riscv: hardwire bits in hideleg and hedeleg, Alistair Francis, 2021/07/12
- [PULL 10/11] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri, Alistair Francis, 2021/07/12
- [PULL 11/11] hw/riscv: opentitan: Add the flash alias, Alistair Francis, 2021/07/12
- Re: [PULL 00/11] riscv-to-apply queue, Peter Maydell, 2021/07/13