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Re: [PULL 00/11] riscv-to-apply queue
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From: |
Alistair Francis |
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Subject: |
Re: [PULL 00/11] riscv-to-apply queue |
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Date: |
Thu, 15 Jul 2021 16:56:55 +1000 |
On Wed, Jul 14, 2021 at 4:01 AM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Mon, 12 Jul 2021 at 23:53, Alistair Francis <alistair.francis@wdc.com>
> wrote:
> >
> > The following changes since commit 57e28d34c0cb04abf7683ac6a12c87ede447c320:
> >
> > Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210708'
> > into staging (2021-07-12 19:15:11 +0100)
> >
> > are available in the Git repository at:
> >
> > git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210712
> >
> > for you to fetch changes up to d6b87906f09f72a837dc68c33bfc3d913ef74b7d:
> >
> > hw/riscv: opentitan: Add the flash alias (2021-07-13 08:47:52 +1000)
> >
> > ----------------------------------------------------------------
> > Fourth RISC-V PR for 6.1 release
> >
> > - Code cleanups
> > - Documentation improvements
> > - Hypervisor extension improvements with hideleg and hedeleg
> > - sifive_u fixes
> > - OpenTitan register layout updates
>
> Hi; this fails to compile on some hosts:
>
> ../../target/riscv/csr.c:437:48: error: initializer element is not constant
> static const target_ulong vs_delegable_excps = delegable_excps &
> ^~~~~~~~~~~~~~~
>
>
> That happens on s390x, x86-64, aarch32, NetBSD. I think this is
> "gcc older than gcc 8 is stricter about what it allows as a
> constant expression". If I understand the GCC bugzilla issue I
> ran into via a bit of googling, the C spec is quite limiting in
> what it considers to be a "constant expression", and in particular
> "some other variable with the 'const' attribute" isn't one.
> The spec does allow compilers the impdef leeway to allow a wider
> range of things to be constant expressions, and gcc 8 is cleverer
> here than gcc 7 was.
>
> If delegable_excps was a #define rather than a 'const' variable
> it would be OK here, I think.
Sorry about that, sending a new version.
Alistair
>
> thanks
> -- PMM
>
- [PULL 03/11] docs/system: riscv: Fix CLINT name in the sifive_u doc, (continued)
- [PULL 03/11] docs/system: riscv: Fix CLINT name in the sifive_u doc, Alistair Francis, 2021/07/12
- [PULL 02/11] target/riscv: csr: Remove redundant check in fp csr read/write routines, Alistair Francis, 2021/07/12
- [PULL 08/11] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned, Alistair Francis, 2021/07/12
- [PULL 04/11] docs/system: riscv: Add documentation for virt machine, Alistair Francis, 2021/07/12
- [PULL 09/11] char: ibex_uart: Update the register layout, Alistair Francis, 2021/07/12
- [PULL 06/11] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot, Alistair Francis, 2021/07/12
- [PULL 05/11] target/riscv: hardwire bits in hideleg and hedeleg, Alistair Francis, 2021/07/12
- [PULL 10/11] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri, Alistair Francis, 2021/07/12
- [PULL 11/11] hw/riscv: opentitan: Add the flash alias, Alistair Francis, 2021/07/12
- Re: [PULL 00/11] riscv-to-apply queue, Peter Maydell, 2021/07/13
- Re: [PULL 00/11] riscv-to-apply queue,
Alistair Francis <=