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[PULL 07/14] target/alpha: Use tcg_constant_i64 for zero and lit
From: |
Richard Henderson |
Subject: |
[PULL 07/14] target/alpha: Use tcg_constant_i64 for zero and lit |
Date: |
Tue, 13 Jul 2021 09:42:04 -0700 |
These constant temps do not need to be freed, and
therefore need less bookkeeping from tcg producers.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/translate.c | 16 ++--------------
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 64c4865dda..58c0e08c0c 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -66,8 +66,6 @@ struct DisasContext {
/* Temporaries for $31 and $f31 as source and destination. */
TCGv zero;
TCGv sink;
- /* Temporary for immediate constants. */
- TCGv lit;
};
/* Target-specific return values from translate_one, indicating the
@@ -157,7 +155,7 @@ void alpha_translate_init(void)
static TCGv load_zero(DisasContext *ctx)
{
if (!ctx->zero) {
- ctx->zero = tcg_const_i64(0);
+ ctx->zero = tcg_constant_i64(0);
}
return ctx->zero;
}
@@ -177,14 +175,6 @@ static void free_context_temps(DisasContext *ctx)
tcg_temp_free(ctx->sink);
ctx->sink = NULL;
}
- if (ctx->zero) {
- tcg_temp_free(ctx->zero);
- ctx->zero = NULL;
- }
- if (ctx->lit) {
- tcg_temp_free(ctx->lit);
- ctx->lit = NULL;
- }
}
static TCGv load_gpr(DisasContext *ctx, unsigned reg)
@@ -200,8 +190,7 @@ static TCGv load_gpr_lit(DisasContext *ctx, unsigned reg,
uint8_t lit, bool islit)
{
if (islit) {
- ctx->lit = tcg_const_i64(lit);
- return ctx->lit;
+ return tcg_constant_i64(lit);
} else if (likely(reg < 31)) {
return ctx->ir[reg];
} else {
@@ -2992,7 +2981,6 @@ static void alpha_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cpu)
ctx->zero = NULL;
ctx->sink = NULL;
- ctx->lit = NULL;
/* Bound the number of insns to execute to those left on the page. */
bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
--
2.25.1
- [PULL 00/14] misc translator patch queue, Richard Henderson, 2021/07/13
- [PULL 01/14] target/i386: Tidy hw_breakpoint_remove, Richard Henderson, 2021/07/13
- [PULL 03/14] target/i386: Split out do_fninit, Richard Henderson, 2021/07/13
- [PULL 02/14] target/i386: Trivial code motion and code style fix, Richard Henderson, 2021/07/13
- [PULL 05/14] target/alpha: Store set into rx flag, Richard Henderson, 2021/07/13
- [PULL 06/14] target/alpha: Use dest_sink for HW_RET temporary, Richard Henderson, 2021/07/13
- [PULL 04/14] target/i386: Correct implementation for FCS, FIP, FDS and FDP, Richard Henderson, 2021/07/13
- [PULL 07/14] target/alpha: Use tcg_constant_i64 for zero and lit,
Richard Henderson <=
- [PULL 11/14] target/openrisc: Cache constant 0 in DisasContext, Richard Henderson, 2021/07/13
- [PULL 08/14] target/alpha: Use tcg_constant_* elsewhere, Richard Henderson, 2021/07/13
- [PULL 10/14] target/openrisc: Use tcg_constant_tl for dc->R0, Richard Henderson, 2021/07/13
- [PULL 09/14] target/openrisc: Use tcg_constant_*, Richard Henderson, 2021/07/13
- [PULL 12/14] target/openrisc: Use dc->zero in gen_add, gen_addc, Richard Henderson, 2021/07/13
- [PULL 14/14] target/hppa: Clean up DisasCond, Richard Henderson, 2021/07/13
- [PULL 13/14] target/hppa: Use tcg_constant_*, Richard Henderson, 2021/07/13
- Re: [PULL 00/14] misc translator patch queue, Peter Maydell, 2021/07/14