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[PULL 11/14] target/openrisc: Cache constant 0 in DisasContext
From: |
Richard Henderson |
Subject: |
[PULL 11/14] target/openrisc: Cache constant 0 in DisasContext |
Date: |
Tue, 13 Jul 2021 09:42:08 -0700 |
We are virtually certain to have fetched constant 0 once, at the
beginning of the TB, so we might as well use it elsewhere.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/openrisc/translate.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 2db529b7de..6aba4c2ffc 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -52,6 +52,8 @@ typedef struct DisasContext {
/* The temporary corresponding to register 0 for this compilation. */
TCGv R0;
+ /* The constant zero. */
+ TCGv zero;
} DisasContext;
static inline bool is_user(DisasContext *dc)
@@ -536,10 +538,8 @@ static bool trans_l_extbz(DisasContext *dc, arg_da *a)
static bool trans_l_cmov(DisasContext *dc, arg_dab *a)
{
- TCGv zero = tcg_constant_tl(0);
-
check_r0_write(dc, a->d);
- tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, zero,
+ tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, dc->zero,
cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
@@ -630,9 +630,8 @@ static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond
cond)
target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
TCGv t_next = tcg_constant_tl(dc->base.pc_next + 8);
TCGv t_true = tcg_constant_tl(tmp_pc);
- TCGv t_zero = tcg_constant_tl(0);
- tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, t_zero, t_true, t_next);
+ tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, dc->zero, t_true, t_next);
dc->delayed_branch = 2;
}
@@ -1594,8 +1593,9 @@ static void openrisc_tr_tb_start(DisasContextBase *db,
CPUState *cs)
/* Allow the TCG optimizer to see that R0 == 0,
when it's true, which is the common case. */
+ dc->zero = tcg_constant_tl(0);
if (dc->tb_flags & TB_FLAGS_R0_0) {
- dc->R0 = tcg_constant_tl(0);
+ dc->R0 = dc->zero;
} else {
dc->R0 = cpu_regs[0];
}
--
2.25.1
- [PULL 00/14] misc translator patch queue, Richard Henderson, 2021/07/13
- [PULL 01/14] target/i386: Tidy hw_breakpoint_remove, Richard Henderson, 2021/07/13
- [PULL 03/14] target/i386: Split out do_fninit, Richard Henderson, 2021/07/13
- [PULL 02/14] target/i386: Trivial code motion and code style fix, Richard Henderson, 2021/07/13
- [PULL 05/14] target/alpha: Store set into rx flag, Richard Henderson, 2021/07/13
- [PULL 06/14] target/alpha: Use dest_sink for HW_RET temporary, Richard Henderson, 2021/07/13
- [PULL 04/14] target/i386: Correct implementation for FCS, FIP, FDS and FDP, Richard Henderson, 2021/07/13
- [PULL 07/14] target/alpha: Use tcg_constant_i64 for zero and lit, Richard Henderson, 2021/07/13
- [PULL 11/14] target/openrisc: Cache constant 0 in DisasContext,
Richard Henderson <=
- [PULL 08/14] target/alpha: Use tcg_constant_* elsewhere, Richard Henderson, 2021/07/13
- [PULL 10/14] target/openrisc: Use tcg_constant_tl for dc->R0, Richard Henderson, 2021/07/13
- [PULL 09/14] target/openrisc: Use tcg_constant_*, Richard Henderson, 2021/07/13
- [PULL 12/14] target/openrisc: Use dc->zero in gen_add, gen_addc, Richard Henderson, 2021/07/13
- [PULL 14/14] target/hppa: Clean up DisasCond, Richard Henderson, 2021/07/13
- [PULL 13/14] target/hppa: Use tcg_constant_*, Richard Henderson, 2021/07/13
- Re: [PULL 00/14] misc translator patch queue, Peter Maydell, 2021/07/14