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[PULL v2 08/12] hw/riscv: sifive_u: Make sure firmware info is 8-byte al
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From: |
Alistair Francis |
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Subject: |
[PULL v2 08/12] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned |
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Date: |
Thu, 15 Jul 2021 00:16:36 -0700 |
From: Bin Meng <bmeng.cn@gmail.com>
Currently the firmware dynamic info (fw_dyn) is put right after
the reset vector, which is not 8-byte aligned on RV64. OpenSBI
fw_dynamic uses ld to read contents from 'struct fw_dynamic_info',
which expects fw_dyn to be on the 8-byte boundary, otherwise the
misaligned load exception may happen. Fortunately this does not
cause any issue on QEMU, as QEMU does support misaligned load.
RV32 does not have any issue as it is 4-byte aligned already.
Change to make sure it is 8-byte aligned which works for both
RV32 and RV64.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210708143319.10441-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e75ca38783..87bbd10b21 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -602,10 +602,10 @@ static void sifive_u_machine_init(MachineState *machine)
}
/* reset vector */
- uint32_t reset_vec[11] = {
+ uint32_t reset_vec[12] = {
s->msel, /* MSEL pin state */
0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
- 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
+ 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */
0xf1402573, /* csrr a0, mhartid */
0,
0,
@@ -613,6 +613,7 @@ static void sifive_u_machine_init(MachineState *machine)
start_addr, /* start: .dword */
start_addr_hi32,
fdt_load_addr, /* fdt_laddr: .dword */
+ 0x00000000,
0x00000000,
/* fw_dyn: */
};
--
2.31.1
- [PULL v2 00/12] riscv-to-apply queue, Alistair Francis, 2021/07/15
- [PULL v2 01/12] target/riscv: pmp: Fix some typos, Alistair Francis, 2021/07/15
- [PULL v2 02/12] target/riscv: csr: Remove redundant check in fp csr read/write routines, Alistair Francis, 2021/07/15
- [PULL v2 03/12] docs/system: riscv: Fix CLINT name in the sifive_u doc, Alistair Francis, 2021/07/15
- [PULL v2 04/12] docs/system: riscv: Add documentation for virt machine, Alistair Francis, 2021/07/15
- [PULL v2 05/12] target/riscv: hardwire bits in hideleg and hedeleg, Alistair Francis, 2021/07/15
- [PULL v2 06/12] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot, Alistair Francis, 2021/07/15
- [PULL v2 07/12] hw/riscv: sifive_u: Correct the CLINT timebase frequency, Alistair Francis, 2021/07/15
- [PULL v2 08/12] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned,
Alistair Francis <=
- [PULL v2 09/12] char: ibex_uart: Update the register layout, Alistair Francis, 2021/07/15
- [PULL v2 11/12] hw/riscv: opentitan: Add the flash alias, Alistair Francis, 2021/07/15
- [PULL v2 10/12] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri, Alistair Francis, 2021/07/15
- [PULL v2 12/12] hw/riscv/boot: Check the error of fdt_pack(), Alistair Francis, 2021/07/15
- Re: [PULL v2 00/12] riscv-to-apply queue, Peter Maydell, 2021/07/16