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[PULL v2 12/12] hw/riscv/boot: Check the error of fdt_pack()
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From: |
Alistair Francis |
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Subject: |
[PULL v2 12/12] hw/riscv/boot: Check the error of fdt_pack() |
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Date: |
Thu, 15 Jul 2021 00:16:40 -0700 |
Coverity reports that we don't check the error result of fdt_pack(), so
let's save the result and assert that it is 0.
Fixes: Coverity CID 1458136
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
07325315b49d5555269f76094e4bc5296e0643b9.1626303527.git.alistair.francis@wdc.com
---
hw/riscv/boot.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 0d38bb7426..993bf89064 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -182,7 +182,7 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t
mem_size, void *fdt)
{
uint32_t temp, fdt_addr;
hwaddr dram_end = dram_base + mem_size;
- int fdtsize = fdt_totalsize(fdt);
+ int ret, fdtsize = fdt_totalsize(fdt);
if (fdtsize <= 0) {
error_report("invalid device-tree");
@@ -198,7 +198,9 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t
mem_size, void *fdt)
temp = MIN(dram_end, 3072 * MiB);
fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
- fdt_pack(fdt);
+ ret = fdt_pack(fdt);
+ /* Should only fail if we've built a corrupted tree */
+ g_assert(ret == 0);
/* copy in the device tree */
qemu_fdt_dumpdtb(fdt, fdtsize);
--
2.31.1
- [PULL v2 02/12] target/riscv: csr: Remove redundant check in fp csr read/write routines, (continued)
- [PULL v2 02/12] target/riscv: csr: Remove redundant check in fp csr read/write routines, Alistair Francis, 2021/07/15
- [PULL v2 03/12] docs/system: riscv: Fix CLINT name in the sifive_u doc, Alistair Francis, 2021/07/15
- [PULL v2 04/12] docs/system: riscv: Add documentation for virt machine, Alistair Francis, 2021/07/15
- [PULL v2 05/12] target/riscv: hardwire bits in hideleg and hedeleg, Alistair Francis, 2021/07/15
- [PULL v2 06/12] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot, Alistair Francis, 2021/07/15
- [PULL v2 07/12] hw/riscv: sifive_u: Correct the CLINT timebase frequency, Alistair Francis, 2021/07/15
- [PULL v2 08/12] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned, Alistair Francis, 2021/07/15
- [PULL v2 09/12] char: ibex_uart: Update the register layout, Alistair Francis, 2021/07/15
- [PULL v2 11/12] hw/riscv: opentitan: Add the flash alias, Alistair Francis, 2021/07/15
- [PULL v2 10/12] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri, Alistair Francis, 2021/07/15
- [PULL v2 12/12] hw/riscv/boot: Check the error of fdt_pack(),
Alistair Francis <=
- Re: [PULL v2 00/12] riscv-to-apply queue, Peter Maydell, 2021/07/16