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[PATCH for-6.2 01/53] target/arm: Note that we handle VMOVL as a special
From: |
Peter Maydell |
Subject: |
[PATCH for-6.2 01/53] target/arm: Note that we handle VMOVL as a special case of VSHLL |
Date: |
Thu, 29 Jul 2021 12:14:20 +0100 |
Although the architecture doesn't define it as an alias, VMOVL
(vector move long) is encoded as a VSHLL with a zero shift.
Add a comment in the decode file noting that we handle VMOVL
as part of VSHLL.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/mve.decode | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 595d97568eb..fa9d921f933 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -364,6 +364,8 @@ VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1
... 0 @2_shr_h
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
+# Note that VMOVL is encoded as "VSHLL with a zero shift count"; we
+# implement it that way rather than special-casing it in the decode.
VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
--
2.20.1
- [PATCH for-6.2 00/53] target/arm: MVE slices 3 and 4, Peter Maydell, 2021/07/29
- [PATCH for-6.2 01/53] target/arm: Note that we handle VMOVL as a special case of VSHLL,
Peter Maydell <=
- [PATCH for-6.2 03/53] target/arm: Fix MVE VSLI by 0 and VSRI by <dt>, Peter Maydell, 2021/07/29
- [PATCH for-6.2 02/53] target/arm: Print MVE VPR in CPU dumps, Peter Maydell, 2021/07/29
- [PATCH for-6.2 04/53] target/arm: Fix signed VADDV, Peter Maydell, 2021/07/29
- [PATCH for-6.2 05/53] target/arm: Fix mask handling for MVE narrowing operations, Peter Maydell, 2021/07/29
- [PATCH for-6.2 06/53] target/arm: Fix 48-bit saturating shifts, Peter Maydell, 2021/07/29
- [PATCH for-6.2 09/53] target/arm: Factor out mve_eci_mask(), Peter Maydell, 2021/07/29
- [PATCH for-6.2 07/53] target/arm: Fix MVE 48-bit SQRSHRL for small right shifts, Peter Maydell, 2021/07/29
- [PATCH for-6.2 08/53] target/arm: Fix calculation of LTP mask when LR is 0, Peter Maydell, 2021/07/29