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[PULL 07/44] target/arm: Fix MVE 48-bit SQRSHRL for small right shifts
From: |
Peter Maydell |
Subject: |
[PULL 07/44] target/arm: Fix MVE 48-bit SQRSHRL for small right shifts |
Date: |
Wed, 25 Aug 2021 11:34:57 +0100 |
We got an edge case wrong in the 48-bit SQRSHRL implementation: if
the shift is to the right, although it always makes the result
smaller than the input value it might not be within the 48-bit range
the result is supposed to be if the input had some bits in [63..48]
set and the shift didn't bring all of those within the [47..0] range.
Handle this similarly to the way we already do for this case in
do_uqrshl48_d(): extend the calculated result from 48 bits,
and return that if not saturating or if it doesn't change the
result; otherwise fall through to return a saturated value.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/mve_helper.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 5730b48f35e..1a4b2ef8075 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -1563,6 +1563,8 @@ uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t
n, uint32_t shift)
static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
bool round, uint32_t *sat)
{
+ int64_t val, extval;
+
if (shift <= -48) {
/* Rounding the sign bit always produces 0. */
if (round) {
@@ -1572,9 +1574,14 @@ static inline int64_t do_sqrshl48_d(int64_t src, int64_t
shift,
} else if (shift < 0) {
if (round) {
src >>= -shift - 1;
- return (src >> 1) + (src & 1);
+ val = (src >> 1) + (src & 1);
+ } else {
+ val = src >> -shift;
+ }
+ extval = sextract64(val, 0, 48);
+ if (!sat || val == extval) {
+ return extval;
}
- return src >> -shift;
} else if (shift < 48) {
int64_t extval = sextract64(src << shift, 0, 48);
if (!sat || src == (extval >> shift)) {
--
2.20.1
- [PULL 00/44] target-arm queue, Peter Maydell, 2021/08/25
- [PULL 01/44] target/arm: Note that we handle VMOVL as a special case of VSHLL, Peter Maydell, 2021/08/25
- [PULL 02/44] target/arm: Print MVE VPR in CPU dumps, Peter Maydell, 2021/08/25
- [PULL 03/44] target/arm: Fix MVE VSLI by 0 and VSRI by <dt>, Peter Maydell, 2021/08/25
- [PULL 06/44] target/arm: Fix 48-bit saturating shifts, Peter Maydell, 2021/08/25
- [PULL 04/44] target/arm: Fix signed VADDV, Peter Maydell, 2021/08/25
- [PULL 09/44] target/arm: Factor out mve_eci_mask(), Peter Maydell, 2021/08/25
- [PULL 05/44] target/arm: Fix mask handling for MVE narrowing operations, Peter Maydell, 2021/08/25
- [PULL 07/44] target/arm: Fix MVE 48-bit SQRSHRL for small right shifts,
Peter Maydell <=
- [PULL 08/44] target/arm: Fix calculation of LTP mask when LR is 0, Peter Maydell, 2021/08/25
- [PULL 10/44] target/arm: Fix VPT advance when ECI is non-zero, Peter Maydell, 2021/08/25
- [PULL 11/44] target/arm: Fix VLDRB/H/W for predicated elements, Peter Maydell, 2021/08/25
- [PULL 13/44] target/arm: Implement MVE incrementing/decrementing dup insns, Peter Maydell, 2021/08/25
- [PULL 12/44] target/arm: Implement MVE VMULL (polynomial), Peter Maydell, 2021/08/25
- [PULL 14/44] target/arm: Factor out gen_vpst(), Peter Maydell, 2021/08/25
- [PULL 16/44] target/arm: Implement MVE integer vector-vs-scalar comparisons, Peter Maydell, 2021/08/25
- [PULL 15/44] target/arm: Implement MVE integer vector comparisons, Peter Maydell, 2021/08/25
- [PULL 19/44] target/arm: Implement MVE shift-by-scalar, Peter Maydell, 2021/08/25
- [PULL 18/44] target/arm: Implement MVE VMLAS, Peter Maydell, 2021/08/25