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[PULL 11/44] target/arm: Fix VLDRB/H/W for predicated elements
From: |
Peter Maydell |
Subject: |
[PULL 11/44] target/arm: Fix VLDRB/H/W for predicated elements |
Date: |
Wed, 25 Aug 2021 11:35:01 +0100 |
For vector loads, predicated elements are zeroed, instead of
retaining their previous values (as happens for most data
processing operations). This means we need to distinguish
"beat not executed due to ECI" (don't touch destination
element) from "beat executed but predicated out" (zero
destination element).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/mve_helper.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index bc89ce94d5a..be8b9545317 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -146,12 +146,13 @@ static void mve_advance_vpt(CPUARMState *env)
env->v7m.vpr = vpr;
}
-
+/* For loads, predicated lanes are zeroed instead of keeping their old values
*/
#define DO_VLDR(OP, MSIZE, LDTYPE, ESIZE, TYPE) \
void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \
{ \
TYPE *d = vd; \
uint16_t mask = mve_element_mask(env); \
+ uint16_t eci_mask = mve_eci_mask(env); \
unsigned b, e; \
/* \
* R_SXTM allows the dest reg to become UNKNOWN for abandoned \
@@ -159,8 +160,9 @@ static void mve_advance_vpt(CPUARMState *env)
* then take an exception. \
*/ \
for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \
- if (mask & (1 << b)) { \
- d[H##ESIZE(e)] = cpu_##LDTYPE##_data_ra(env, addr, GETPC()); \
+ if (eci_mask & (1 << b)) { \
+ d[H##ESIZE(e)] = (mask & (1 << b)) ? \
+ cpu_##LDTYPE##_data_ra(env, addr, GETPC()) : 0; \
} \
addr += MSIZE; \
} \
--
2.20.1
- [PULL 01/44] target/arm: Note that we handle VMOVL as a special case of VSHLL, (continued)
- [PULL 01/44] target/arm: Note that we handle VMOVL as a special case of VSHLL, Peter Maydell, 2021/08/25
- [PULL 02/44] target/arm: Print MVE VPR in CPU dumps, Peter Maydell, 2021/08/25
- [PULL 03/44] target/arm: Fix MVE VSLI by 0 and VSRI by <dt>, Peter Maydell, 2021/08/25
- [PULL 06/44] target/arm: Fix 48-bit saturating shifts, Peter Maydell, 2021/08/25
- [PULL 04/44] target/arm: Fix signed VADDV, Peter Maydell, 2021/08/25
- [PULL 09/44] target/arm: Factor out mve_eci_mask(), Peter Maydell, 2021/08/25
- [PULL 05/44] target/arm: Fix mask handling for MVE narrowing operations, Peter Maydell, 2021/08/25
- [PULL 07/44] target/arm: Fix MVE 48-bit SQRSHRL for small right shifts, Peter Maydell, 2021/08/25
- [PULL 08/44] target/arm: Fix calculation of LTP mask when LR is 0, Peter Maydell, 2021/08/25
- [PULL 10/44] target/arm: Fix VPT advance when ECI is non-zero, Peter Maydell, 2021/08/25
- [PULL 11/44] target/arm: Fix VLDRB/H/W for predicated elements,
Peter Maydell <=
- [PULL 13/44] target/arm: Implement MVE incrementing/decrementing dup insns, Peter Maydell, 2021/08/25
- [PULL 12/44] target/arm: Implement MVE VMULL (polynomial), Peter Maydell, 2021/08/25
- [PULL 14/44] target/arm: Factor out gen_vpst(), Peter Maydell, 2021/08/25
- [PULL 16/44] target/arm: Implement MVE integer vector-vs-scalar comparisons, Peter Maydell, 2021/08/25
- [PULL 15/44] target/arm: Implement MVE integer vector comparisons, Peter Maydell, 2021/08/25
- [PULL 19/44] target/arm: Implement MVE shift-by-scalar, Peter Maydell, 2021/08/25
- [PULL 18/44] target/arm: Implement MVE VMLAS, Peter Maydell, 2021/08/25
- [PULL 20/44] target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats, Peter Maydell, 2021/08/25
- [PULL 22/44] target/arm: Implement MVE VABAV, Peter Maydell, 2021/08/25
- [PULL 17/44] target/arm: Implement MVE VPSEL, Peter Maydell, 2021/08/25