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[PATCH v3 4/9] escc: introduce escc_hard_reset_chn() for hardware reset
From: |
Mark Cave-Ayland |
Subject: |
[PATCH v3 4/9] escc: introduce escc_hard_reset_chn() for hardware reset |
Date: |
Fri, 3 Sep 2021 12:32:18 +0100 |
This new hardware reset function is to be called for both channels when the
hardware reset bit is written to register WR9. Its initial implementation is
the same as the existing escc_reset_chn() function used for device reset.
Add a new trace event when the guest initiates a hard reset via the WR9 register
to help diagnose guest reset issues.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
hw/char/escc.c | 38 +++++++++++++++++++++++++++++++++++++-
hw/char/trace-events | 1 +
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/hw/char/escc.c b/hw/char/escc.c
index 697f15f383..806f593738 100644
--- a/hw/char/escc.c
+++ b/hw/char/escc.c
@@ -331,6 +331,40 @@ static void escc_soft_reset_chn(ESCCChannelState *s)
clear_queue(s);
}
+static void escc_hard_reset_chn(ESCCChannelState *s)
+{
+ int i;
+
+ s->reg = 0;
+ for (i = 0; i < ESCC_SERIAL_REGS; i++) {
+ s->rregs[i] = 0;
+ s->wregs[i] = 0;
+ }
+ /* 1X divisor, 1 stop bit, no parity */
+ s->wregs[W_TXCTRL1] = TXCTRL1_1STOP;
+ s->wregs[W_MINTR] = MINTR_RST_ALL;
+ /* Synch mode tx clock = TRxC */
+ s->wregs[W_CLOCK] = CLOCK_TRXC;
+ /* PLL disabled */
+ s->wregs[W_MISC2] = MISC2_PLLDIS;
+ /* Enable most interrupts */
+ s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT |
+ EXTINT_TXUNDRN | EXTINT_BRKINT;
+ if (s->disabled) {
+ s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC |
+ STATUS_CTS | STATUS_TXUNDRN;
+ } else {
+ s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN;
+ }
+ s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT;
+
+ s->rx = s->tx = 0;
+ s->rxint = s->txint = 0;
+ s->rxint_under_svc = s->txint_under_svc = 0;
+ s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0;
+ clear_queue(s);
+}
+
static void escc_reset(DeviceState *d)
{
ESCCState *s = ESCC(d);
@@ -589,7 +623,9 @@ static void escc_mem_write(void *opaque, hwaddr addr,
escc_soft_reset_chn(&serial->chn[1]);
return;
case MINTR_RST_ALL:
- escc_reset(DEVICE(serial));
+ trace_escc_hard_reset();
+ escc_hard_reset_chn(&serial->chn[0]);
+ escc_hard_reset_chn(&serial->chn[1]);
return;
}
break;
diff --git a/hw/char/trace-events b/hw/char/trace-events
index 073f98ebe8..b774832af4 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -36,6 +36,7 @@ grlib_apbuart_writel_unknown(uint64_t addr, uint32_t value)
"addr 0x%"PRIx64" va
grlib_apbuart_readl_unknown(uint64_t addr) "addr 0x%"PRIx64
# escc.c
+escc_hard_reset(void) "hard reset"
escc_soft_reset_chn(char channel) "soft reset channel %c"
escc_put_queue(char channel, int b) "channel %c put: 0x%02x"
escc_get_queue(char channel, int val) "channel %c get 0x%02x"
--
2.20.1
- [PATCH v3 0/9] escc: fix reset and R_STATUS when SDLC mode is enabled, Mark Cave-Ayland, 2021/09/03
- [PATCH v3 2/9] escc: reset register values to zero in escc_reset(), Mark Cave-Ayland, 2021/09/03
- [PATCH v3 1/9] escc: checkpatch fixes, Mark Cave-Ayland, 2021/09/03
- [PATCH v3 3/9] escc: introduce escc_soft_reset_chn() for software reset, Mark Cave-Ayland, 2021/09/03
- [PATCH v3 4/9] escc: introduce escc_hard_reset_chn() for hardware reset,
Mark Cave-Ayland <=
- [PATCH v3 6/9] escc: implement hard reset as described in the datasheet, Mark Cave-Ayland, 2021/09/03
- [PATCH v3 5/9] escc: implement soft reset as described in the datasheet, Mark Cave-Ayland, 2021/09/03
- [PATCH v3 7/9] escc: remove register changes from escc_reset_chn(), Mark Cave-Ayland, 2021/09/03
- [PATCH v3 8/9] escc: re-use escc_reset_chn() for soft reset, Mark Cave-Ayland, 2021/09/03
- [PATCH v3 9/9] escc: fix STATUS_SYNC bit in R_STATUS register, Mark Cave-Ayland, 2021/09/03