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[PULL 26/44] target/riscv: Restrict cpu_exec_interrupt() handler to syse
From: |
Richard Henderson |
Subject: |
[PULL 26/44] target/riscv: Restrict cpu_exec_interrupt() handler to sysemu |
Date: |
Mon, 13 Sep 2021 17:14:38 -0700 |
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20210911165434.531552-19-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 5 -----
3 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bf1c899c00..e735e53e26 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -334,7 +334,6 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f,
CPUState *cs,
int cpuid, void *opaque);
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
@@ -362,6 +361,7 @@ void riscv_cpu_list(void);
#define cpu_mmu_index riscv_cpu_mmu_index
#ifndef CONFIG_USER_ONLY
+bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1a2b03d579..13575c1408 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -644,10 +644,10 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
static const struct TCGCPUOps riscv_tcg_ops = {
.initialize = riscv_translate_init,
.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
- .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
.tlb_fill = riscv_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
.do_interrupt = riscv_cpu_do_interrupt,
.do_transaction_failed = riscv_cpu_do_transaction_failed,
.do_unaligned_access = riscv_cpu_do_unaligned_access,
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 968cb8046f..701858d670 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -75,11 +75,9 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
return RISCV_EXCP_NONE; /* indicates no pending interrupt */
}
}
-#endif
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
-#if !defined(CONFIG_USER_ONLY)
if (interrupt_request & CPU_INTERRUPT_HARD) {
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
@@ -90,12 +88,9 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
return true;
}
}
-#endif
return false;
}
-#if !defined(CONFIG_USER_ONLY)
-
/* Return true is floating point support is currently enabled */
bool riscv_cpu_fp_enabled(CPURISCVState *env)
{
--
2.25.1
- [PULL 25/44] target/ppc: Restrict cpu_exec_interrupt() handler to sysemu, (continued)
- [PULL 25/44] target/ppc: Restrict cpu_exec_interrupt() handler to sysemu, Richard Henderson, 2021/09/13
- [PULL 24/44] target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu, Richard Henderson, 2021/09/13
- [PULL 28/44] target/sparc: Restrict cpu_exec_interrupt() handler to sysemu, Richard Henderson, 2021/09/13
- [PULL 14/44] target/alpha: Restrict cpu_exec_interrupt() handler to sysemu, Richard Henderson, 2021/09/13
- [PULL 11/44] target/i386: Simplify TARGET_X86_64 #ifdef'ry, Richard Henderson, 2021/09/13
- [PULL 16/44] target/cris: Restrict cpu_exec_interrupt() handler to sysemu, Richard Henderson, 2021/09/13
- [PULL 13/44] accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt, Richard Henderson, 2021/09/13
- [PULL 17/44] target/hppa: Restrict cpu_exec_interrupt() handler to sysemu, Richard Henderson, 2021/09/13
- [PULL 22/44] target/mips: Restrict cpu_exec_interrupt() handler to sysemu, Richard Henderson, 2021/09/13
- [PULL 20/44] target/m68k: Restrict cpu_exec_interrupt() handler to sysemu, Richard Henderson, 2021/09/13
- [PULL 26/44] target/riscv: Restrict cpu_exec_interrupt() handler to sysemu,
Richard Henderson <=
- [PULL 32/44] user: Remove cpu_get_pic_interrupt() stubs, Richard Henderson, 2021/09/13
- [PULL 27/44] target/sh4: Restrict cpu_exec_interrupt() handler to sysemu, Richard Henderson, 2021/09/13
- [PULL 33/44] user: Mark cpu_loop() with noreturn attribute, Richard Henderson, 2021/09/13
- [PULL 30/44] target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu, Richard Henderson, 2021/09/13
- [PULL 23/44] target/nios2: Restrict cpu_exec_interrupt() handler to sysemu, Richard Henderson, 2021/09/13
- [PULL 19/44] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder, Richard Henderson, 2021/09/13
- [PULL 12/44] target/xtensa: Restrict do_transaction_failed() to sysemu, Richard Henderson, 2021/09/13
- [PULL 35/44] tcg/arm: Remove fallback definition of __ARM_ARCH, Richard Henderson, 2021/09/13
- [PULL 38/44] tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call, Richard Henderson, 2021/09/13