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[PATCH 20/30] tcg/loongarch: Implement setcond ops
From: |
WANG Xuerui |
Subject: |
[PATCH 20/30] tcg/loongarch: Implement setcond ops |
Date: |
Mon, 20 Sep 2021 16:04:41 +0800 |
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
tcg/loongarch/tcg-target.c.inc | 53 ++++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc
index a533a5619d..fb0143474a 100644
--- a/tcg/loongarch/tcg-target.c.inc
+++ b/tcg/loongarch/tcg-target.c.inc
@@ -373,6 +373,52 @@ static void tcg_out_clzctz(TCGContext *s, LoongArchInsn
opc,
tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0);
}
+static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
+ TCGReg arg1, TCGReg arg2)
+{
+ switch (cond) {
+ case TCG_COND_EQ:
+ tcg_out_opc_sub_d(s, ret, arg1, arg2);
+ tcg_out_opc_sltui(s, ret, ret, 1);
+ break;
+ case TCG_COND_NE:
+ tcg_out_opc_sub_d(s, ret, arg1, arg2);
+ tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, ret);
+ break;
+ case TCG_COND_LT:
+ tcg_out_opc_slt(s, ret, arg1, arg2);
+ break;
+ case TCG_COND_GE:
+ tcg_out_opc_slt(s, ret, arg1, arg2);
+ tcg_out_opc_xori(s, ret, ret, 1);
+ break;
+ case TCG_COND_LE:
+ tcg_out_opc_slt(s, ret, arg2, arg1);
+ tcg_out_opc_xori(s, ret, ret, 1);
+ break;
+ case TCG_COND_GT:
+ tcg_out_opc_slt(s, ret, arg2, arg1);
+ break;
+ case TCG_COND_LTU:
+ tcg_out_opc_sltu(s, ret, arg1, arg2);
+ break;
+ case TCG_COND_GEU:
+ tcg_out_opc_sltu(s, ret, arg1, arg2);
+ tcg_out_opc_xori(s, ret, ret, 1);
+ break;
+ case TCG_COND_LEU:
+ tcg_out_opc_sltu(s, ret, arg2, arg1);
+ tcg_out_opc_xori(s, ret, ret, 1);
+ break;
+ case TCG_COND_GTU:
+ tcg_out_opc_sltu(s, ret, arg2, arg1);
+ break;
+ default:
+ g_assert_not_reached();
+ break;
+ }
+}
+
/*
* Branch helpers
*/
@@ -726,6 +772,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_opc_mod_du(s, a0, a1, a2);
break;
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
+ tcg_out_setcond(s, args[3], a0, a1, a2);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
default:
@@ -830,6 +881,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_rem_i64:
case INDEX_op_remu_i32:
case INDEX_op_remu_i64:
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
return C_O1_I2(r, rZ, rZ);
default:
--
2.33.0
- Re: [PATCH 14/30] tcg/loongarch: Implement bswap32_i32/bswap64_i64, (continued)
- [PATCH 04/30] tcg/loongarch: Add generated instruction opcodes and encoding helpers, WANG Xuerui, 2021/09/20
- [PATCH 19/30] tcg/loongarch: Implement br/brcond ops, WANG Xuerui, 2021/09/20
- [PATCH 17/30] tcg/loongarch: Implement neg/add/sub ops, WANG Xuerui, 2021/09/20
- [PATCH 11/30] tcg/loongarch: Implement sign-/zero-extension ops, WANG Xuerui, 2021/09/20
- [PATCH 20/30] tcg/loongarch: Implement setcond ops,
WANG Xuerui <=
- [PATCH 15/30] tcg/loongarch: Implement clz/ctz ops, WANG Xuerui, 2021/09/20
- [PATCH 18/30] tcg/loongarch: Implement mul/mulsh/muluh/div/divu/rem/remu ops, WANG Xuerui, 2021/09/20
- [PATCH 08/30] tcg/loongarch: Implement the memory barrier op, WANG Xuerui, 2021/09/20
- [PATCH 24/30] tcg/loongarch: Implement tcg_target_qemu_prologue, WANG Xuerui, 2021/09/20
- [PATCH 28/30] configure, meson.build: Mark support for 64-bit LoongArch hosts, WANG Xuerui, 2021/09/20