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[PATCH v5 41/67] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu
From: |
Richard Henderson |
Subject: |
[PATCH v5 41/67] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu |
Date: |
Thu, 14 Oct 2021 21:10:27 -0700 |
We have replaced tlb_fill with record_sigsegv for user mode.
Move the declaration to restrict it to system emulation.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/tcg-cpu-ops.h | 22 ++++++++++------------
linux-user/signal.c | 3 ---
2 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 41718b695b..8eadd404c8 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -35,18 +35,6 @@ struct TCGCPUOps {
void (*cpu_exec_enter)(CPUState *cpu);
/** @cpu_exec_exit: Callback for cpu_exec cleanup */
void (*cpu_exec_exit)(CPUState *cpu);
- /**
- * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
- *
- * For system mode, if the access is valid, call tlb_set_page
- * and return true; if the access is invalid, and probe is
- * true, return false; otherwise raise an exception and do
- * not return. For user-only mode, always raise an exception
- * and do not return.
- */
- bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
/** @debug_excp_handler: Callback for handling debug exceptions */
void (*debug_excp_handler)(CPUState *cpu);
@@ -68,6 +56,16 @@ struct TCGCPUOps {
#ifdef CONFIG_SOFTMMU
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
+ /**
+ * @tlb_fill: Handle a softmmu tlb miss
+ *
+ * If the access is valid, call tlb_set_page and return true;
+ * if the access is invalid and probe is true, return false;
+ * otherwise raise an exception and do not return.
+ */
+ bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
/**
* @do_transaction_failed: Callback for handling failed memory transactions
* (ie bus faults or external aborts; not MMU faults)
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 135983747d..9d60abc038 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -697,9 +697,6 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
if (tcg_ops->record_sigsegv) {
tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra);
- } else if (tcg_ops->tlb_fill) {
- tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, ra);
- g_assert_not_reached();
}
force_sig_fault(TARGET_SIGSEGV,
--
2.25.1
- [PATCH v5 23/67] target/arm: Implement arm_cpu_record_sigsegv, (continued)
- [PATCH v5 23/67] target/arm: Implement arm_cpu_record_sigsegv, Richard Henderson, 2021/10/15
- [PATCH v5 25/67] target/hexagon: Remove hexagon_cpu_tlb_fill, Richard Henderson, 2021/10/15
- [PATCH v5 26/67] target/hppa: Make hppa_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/15
- [PATCH v5 28/67] target/m68k: Make m68k_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/15
- [PATCH v5 32/67] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE, Richard Henderson, 2021/10/15
- [PATCH v5 27/67] target/i386: Implement x86_cpu_record_sigsegv, Richard Henderson, 2021/10/15
- [PATCH v5 39/67] target/sparc: Make sparc_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/15
- [PATCH v5 29/67] target/microblaze: Make mb_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/15
- [PATCH v5 40/67] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only, Richard Henderson, 2021/10/15
- [PATCH v5 41/67] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu,
Richard Henderson <=
- [PATCH v5 42/67] Revert "cpu: Move cpu_common_props to hw/core/cpu.c", Richard Henderson, 2021/10/15
- [PATCH v5 44/67] linux-user: Add cpu_loop_exit_sigbus, Richard Henderson, 2021/10/15
- [PATCH v5 43/67] hw/core: Add TCGCPUOps.record_sigbus, Richard Henderson, 2021/10/15
- [PATCH v5 49/67] target/ppc: Move SPR_DSISR setting to powerpc_excp, Richard Henderson, 2021/10/15
- [PATCH v5 45/67] target/alpha: Implement alpha_cpu_record_sigbus, Richard Henderson, 2021/10/15
- [PATCH v5 48/67] target/microblaze: Do not set MO_ALIGN for user-only, Richard Henderson, 2021/10/15
- [PATCH v5 51/67] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu, Richard Henderson, 2021/10/15