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Re: [PATCH v3 21/21] target/riscv: support for 128-bit satp
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From: |
Frédéric Pétrot |
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Subject: |
Re: [PATCH v3 21/21] target/riscv: support for 128-bit satp |
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Date: |
Thu, 21 Oct 2021 13:12:21 +0200 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 |
Le 21/10/2021 à 01:09, Richard Henderson a écrit :
> On 10/19/21 2:48 AM, Frédéric Pétrot wrote:
>> Support for a 128-bit satp. This is a bit more involved than necessary
>> because we took the opportunity to increase the page size to 16kB, and
>> change the page table geometry, which makes the page walk a bit more
>> parametrizable (variables instead of defines).
>> Note that is anyway a necessary step for the merging of the 32-bit and
>> 64-bit riscv versions in a single executable.
>>
>> Signed-off-by: Frédéric Pétrot<frederic.petrot@univ-grenoble-alpes.fr>
>> Co-authored-by: Fabien Portas<fabien.portas@grenoble-inp.org>
>> ---
>> target/riscv/cpu-param.h | 9 +++-
>> target/riscv/cpu_bits.h | 10 ++++
>> target/riscv/cpu_helper.c | 54 ++++++++++++++------
>> target/riscv/csr.c | 105 ++++++++++++++++++++++++++++++++------
>> 4 files changed, 144 insertions(+), 34 deletions(-)
>
> Is there a spec for this? I don't see anything in the 2021-10-06 draft...
Indeed, there is nothing close to be standardized on that matter, so we are
clearly out of bounds, I should probably not have added this in the series.
FWIW, we wrote a small specification of the schemes we implemented.
(https://github.com/fpetrot/128-test/blob/main/kernel/vm_spec_short.pdf).
Frédéric
>
>
> r~--
+---------------------------------------------------------------------------+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.fr |
+---------------------------------------------------------------------------+
- [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions, (continued)
- [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/10/19
- [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/10/19
- [PATCH v3 15/21] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/10/19
- [PATCH v3 20/21] target/riscv: adding 128-bit access functions for some csrs, Frédéric Pétrot, 2021/10/19
- [PATCH v3 21/21] target/riscv: support for 128-bit satp, Frédéric Pétrot, 2021/10/19
- [PATCH v3 17/21] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/10/19
- [PATCH v3 18/21] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/10/19
- [PATCH v3 16/21] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/10/19
- [PATCH v3 19/21] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/10/19