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[PULL 05/18] hw/riscv: virt: Use the PLIC config helper function
From: |
Alistair Francis |
Subject: |
[PULL 05/18] hw/riscv: virt: Use the PLIC config helper function |
Date: |
Thu, 28 Oct 2021 14:43:29 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211022060133.3045020-5-alistair.francis@opensource.wdc.com
---
hw/riscv/virt.c | 20 +-------------------
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 28a5909a3b..3af074148e 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -748,24 +748,6 @@ static FWCfgState *create_fw_cfg(const MachineState *mc)
return fw_cfg;
}
-/*
- * Return the per-socket PLIC hart topology configuration string
- * (caller must free with g_free())
- */
-static char *plic_hart_config_string(int hart_count)
-{
- g_autofree const char **vals = g_new(const char *, hart_count + 1);
- int i;
-
- for (i = 0; i < hart_count; i++) {
- vals[i] = "MS";
- }
- vals[i] = NULL;
-
- /* g_strjoinv() obliges us to cast away const here */
- return g_strjoinv(",", (char **)vals);
-}
-
static void virt_machine_init(MachineState *machine)
{
const MemMapEntry *memmap = virt_memmap;
@@ -839,7 +821,7 @@ static void virt_machine_init(MachineState *machine)
}
/* Per-socket PLIC hart topology configuration string */
- plic_hart_config = plic_hart_config_string(hart_count);
+ plic_hart_config = riscv_plic_hart_config_string(hart_count);
/* Per-socket PLIC */
s->plic[i] = sifive_plic_create(
--
2.31.1
- [PULL 00/18] riscv-to-apply queue, Alistair Francis, 2021/10/28
- [PULL 01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration, Alistair Francis, 2021/10/28
- [PULL 02/18] hw/riscv: boot: Add a PLIC config string function, Alistair Francis, 2021/10/28
- [PULL 04/18] hw/riscv: microchip_pfsoc: Use the PLIC config helper function, Alistair Francis, 2021/10/28
- [PULL 05/18] hw/riscv: virt: Use the PLIC config helper function,
Alistair Francis <=
- [PULL 03/18] hw/riscv: sifive_u: Use the PLIC config helper function, Alistair Francis, 2021/10/28
- [PULL 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses, Alistair Francis, 2021/10/28
- [PULL 07/18] target/riscv: Add J-extension into RISC-V, Alistair Francis, 2021/10/28
- [PULL 08/18] target/riscv: Add CSR defines for RISC-V PM extension, Alistair Francis, 2021/10/28
- [PULL 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode, Alistair Francis, 2021/10/28
- [PULL 10/18] target/riscv: Add J extension state description, Alistair Francis, 2021/10/28
- [PULL 11/18] target/riscv: Print new PM CSRs in QEMU logs, Alistair Francis, 2021/10/28
- [PULL 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alistair Francis, 2021/10/28
- [PULL 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension, Alistair Francis, 2021/10/28
- [PULL 14/18] target/riscv: Allow experimental J-ext to be turned on, Alistair Francis, 2021/10/28