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[PULL 11/18] target/riscv: Print new PM CSRs in QEMU logs
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From: |
Alistair Francis |
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Subject: |
[PULL 11/18] target/riscv: Print new PM CSRs in QEMU logs |
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Date: |
Thu, 28 Oct 2021 14:43:35 +1000 |
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211025173609.2724490-6-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6b767a4a0b..16fac64806 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -271,6 +271,13 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
int flags)
CSR_MSCRATCH,
CSR_SSCRATCH,
CSR_SATP,
+ CSR_MMTE,
+ CSR_UPMBASE,
+ CSR_UPMMASK,
+ CSR_SPMBASE,
+ CSR_SPMMASK,
+ CSR_MPMBASE,
+ CSR_MPMMASK,
};
for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
--
2.31.1
- [PULL 01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration, (continued)
- [PULL 01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration, Alistair Francis, 2021/10/28
- [PULL 02/18] hw/riscv: boot: Add a PLIC config string function, Alistair Francis, 2021/10/28
- [PULL 04/18] hw/riscv: microchip_pfsoc: Use the PLIC config helper function, Alistair Francis, 2021/10/28
- [PULL 05/18] hw/riscv: virt: Use the PLIC config helper function, Alistair Francis, 2021/10/28
- [PULL 03/18] hw/riscv: sifive_u: Use the PLIC config helper function, Alistair Francis, 2021/10/28
- [PULL 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses, Alistair Francis, 2021/10/28
- [PULL 07/18] target/riscv: Add J-extension into RISC-V, Alistair Francis, 2021/10/28
- [PULL 08/18] target/riscv: Add CSR defines for RISC-V PM extension, Alistair Francis, 2021/10/28
- [PULL 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode, Alistair Francis, 2021/10/28
- [PULL 10/18] target/riscv: Add J extension state description, Alistair Francis, 2021/10/28
- [PULL 11/18] target/riscv: Print new PM CSRs in QEMU logs,
Alistair Francis <=
- [PULL 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alistair Francis, 2021/10/28
- [PULL 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension, Alistair Francis, 2021/10/28
- [PULL 14/18] target/riscv: Allow experimental J-ext to be turned on, Alistair Francis, 2021/10/28
- [PULL 15/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin, Alistair Francis, 2021/10/28
- [PULL 16/18] target/riscv: change the api for RVF/RVD fmin/fmax, Alistair Francis, 2021/10/28
[PULL 17/18] target/riscv: fix VS interrupts forwarding to HS, Alistair Francis, 2021/10/28