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[PATCH v3 15/32] target/mips: Convert MSA FILL opcode to decodetree
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v3 15/32] target/mips: Convert MSA FILL opcode to decodetree |
Date: |
Thu, 28 Oct 2021 23:08:26 +0200 |
Convert the FILL opcode (Vector Fill from GPR) to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v3:
- Return false if BITS != 64 && DF_DOUBLE instead of raising exception
---
target/mips/tcg/msa.decode | 2 ++
target/mips/tcg/msa_translate.c | 31 +++++++++++++++++++------------
2 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 33288b50355..bcbc573deec 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -27,6 +27,7 @@
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
+@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0
df=%2r_df_w
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i
@@ -82,6 +83,7 @@ BNZ 010001 111 .. ..... ................
@bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ FILL 011110 11000000 .. ..... ..... 011110 @2r
FCLASS 011110 110010000 . ..... ..... 011110 @2rf
FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf
FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 477eba49ac4..1894d779196 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -61,7 +61,6 @@ enum {
OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC,
/* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
- OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R,
OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R,
OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R,
OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R,
@@ -1845,17 +1844,6 @@ static void gen_msa_2r(DisasContext *ctx)
TCGv_i32 tws = tcg_const_i32(ws);
switch (MASK_MSA_2R(ctx->opcode)) {
- case OPC_FILL_df:
-#if !defined(TARGET_MIPS64)
- /* Double format valid only for MIPS64 */
- if (df == DF_DOUBLE) {
- gen_reserved_instruction(ctx);
- break;
- }
-#endif
- gen_helper_msa_fill_df(cpu_env, tcg_constant_i32(df),
- twd, tws); /* trs */
- break;
case OPC_NLOC_df:
switch (df) {
case DF_BYTE:
@@ -1914,6 +1902,25 @@ static void gen_msa_2r(DisasContext *ctx)
tcg_temp_free_i32(tws);
}
+static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
+{
+ if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) {
+ /* Double format valid only for MIPS64 */
+ return false;
+ }
+
+ if (!check_msa_enabled(ctx)) {
+ return true;
+ }
+
+ gen_helper_msa_fill_df(cpu_env,
+ tcg_constant_i32(a->df),
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws));
+
+ return true;
+}
+
static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a,
gen_helper_piii *gen_msa_2rf)
{
--
2.31.1
- [PATCH v3 05/32] target/mips: Have check_msa_access() return a boolean, (continued)
- [PATCH v3 05/32] target/mips: Have check_msa_access() return a boolean, Philippe Mathieu-Daudé, 2021/10/28
- [PATCH v3 06/32] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum, Philippe Mathieu-Daudé, 2021/10/28
- [PATCH v3 07/32] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v, Philippe Mathieu-Daudé, 2021/10/28
- [PATCH v3 08/32] target/mips: Convert MSA LDI opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/28
- [PATCH v3 09/32] target/mips: Convert MSA I5 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/28
- [PATCH v3 11/32] target/mips: Convert MSA SHF opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/28
- [PATCH v3 12/32] target/mips: Convert MSA I8 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/28
- [PATCH v3 10/32] target/mips: Convert MSA BIT instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/28
- [PATCH v3 13/32] target/mips: Convert MSA load/store instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/28
- [PATCH v3 15/32] target/mips: Convert MSA FILL opcode to decodetree,
Philippe Mathieu-Daudé <=
- [PATCH v3 14/32] target/mips: Convert MSA 2RF instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/28
- [PATCH v3 16/32] target/mips: Convert MSA 2R instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/28
- [PATCH v3 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF), Philippe Mathieu-Daudé, 2021/10/28
- [PATCH v3 17/32] target/mips: Convert MSA VEC instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/28
- [PATCH v3 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD), Philippe Mathieu-Daudé, 2021/10/28
- [PATCH v3 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4), Philippe Mathieu-Daudé, 2021/10/28