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[PATCH v7 42/60] hw/core: Add TCGCPUOps.record_sigbus
From: |
Richard Henderson |
Subject: |
[PATCH v7 42/60] hw/core: Add TCGCPUOps.record_sigbus |
Date: |
Mon, 1 Nov 2021 13:27:11 -0400 |
Add a new user-only interface for updating cpu state before
raising a signal. This will take the place of do_unaligned_access
for user-only and should result in less boilerplate for each guest.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/tcg-cpu-ops.h | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 8eadd404c8..e13898553a 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -135,6 +135,29 @@ struct TCGCPUOps {
void (*record_sigsegv)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
bool maperr, uintptr_t ra);
+ /**
+ * record_sigbus:
+ * @cpu: cpu context
+ * @addr: misaligned guest address
+ * @access_type: access was read/write/execute
+ * @ra: host pc for unwinding
+ *
+ * We are about to raise SIGBUS with si_code BUS_ADRALN,
+ * and si_addr set for @addr. Record anything further needed
+ * for the signal ucontext_t.
+ *
+ * If the emulated kernel does not provide the signal handler with
+ * anything besides the user context registers, and the siginfo_t,
+ * then this hook need do nothing and may be omitted.
+ * Otherwise, record the data and return; the caller will raise
+ * the signal, unwind the cpu state, and return to the main loop.
+ *
+ * If it is simpler to re-use the sysemu do_unaligned_access code,
+ * @ra is provided so that a "normal" cpu exception can be raised.
+ * In this case, the signal must be raised by the architecture cpu_loop.
+ */
+ void (*record_sigbus)(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type, uintptr_t ra);
#endif /* CONFIG_SOFTMMU */
#endif /* NEED_CPU_H */
--
2.25.1
- [PATCH v7 24/60] target/cris: Make cris_cpu_tlb_fill sysemu only, (continued)
- [PATCH v7 24/60] target/cris: Make cris_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/01
- [PATCH v7 32/60] linux-user/openrisc: Abort for EXCP_RANGE, EXCP_FPE, Richard Henderson, 2021/11/01
- [PATCH v7 36/60] target/s390x: Use probe_access_flags in s390_probe_access, Richard Henderson, 2021/11/01
- [PATCH v7 37/60] target/s390x: Implement s390_cpu_record_sigsegv, Richard Henderson, 2021/11/01
- [PATCH v7 35/60] target/riscv: Make riscv_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/01
- [PATCH v7 25/60] target/hexagon: Remove hexagon_cpu_tlb_fill, Richard Henderson, 2021/11/01
- [PATCH v7 38/60] target/sh4: Make sh4_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/01
- [PATCH v7 33/60] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/01
- [PATCH v7 23/60] target/arm: Implement arm_cpu_record_sigsegv, Richard Henderson, 2021/11/01
- [PATCH v7 29/60] target/microblaze: Make mb_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/01
- [PATCH v7 42/60] hw/core: Add TCGCPUOps.record_sigbus,
Richard Henderson <=
- [PATCH v7 40/60] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only, Richard Henderson, 2021/11/01
- [PATCH v7 44/60] target/alpha: Implement alpha_cpu_record_sigbus, Richard Henderson, 2021/11/01
- [PATCH v7 45/60] target/arm: Implement arm_cpu_record_sigbus, Richard Henderson, 2021/11/01
- [PATCH v7 47/60] target/microblaze: Do not set MO_ALIGN for user-only, Richard Henderson, 2021/11/01
- [PATCH v7 48/60] target/ppc: Move SPR_DSISR setting to powerpc_excp, Richard Henderson, 2021/11/01
- [PATCH v7 50/60] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu, Richard Henderson, 2021/11/01
- [PATCH v7 41/60] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu, Richard Henderson, 2021/11/01
- [PATCH v7 43/60] linux-user: Add cpu_loop_exit_sigbus, Richard Henderson, 2021/11/01
- [PATCH v7 51/60] linux-user/ppc: Remove POWERPC_EXCP_ALIGN handling, Richard Henderson, 2021/11/01
- [PATCH v7 46/60] linux-user/hppa: Remove EXCP_UNALIGN handling, Richard Henderson, 2021/11/01