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[PATCH 07/35] softfloat: Add flag specific to signaling nans
From: |
Richard Henderson |
Subject: |
[PATCH 07/35] softfloat: Add flag specific to signaling nans |
Date: |
Fri, 19 Nov 2021 17:04:34 +0100 |
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat.c | 4 +++-
fpu/softfloat-parts.c.inc | 18 ++++++++++++------
3 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 9ca50e930b..8abd9ab4ec 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -158,6 +158,7 @@ enum {
float_flag_invalid_zdz = 0x0400, /* 0 / 0 */
float_flag_invalid_sqrt = 0x0800, /* sqrt(-x) */
float_flag_invalid_cvti = 0x1000, /* non-nan to integer */
+ float_flag_invalid_snan = 0x2000, /* any operand was snan */
};
/*
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 9a28720d82..834ed3a054 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -2543,8 +2543,10 @@ floatx80 floatx80_mod(floatx80 a, floatx80 b,
float_status *status)
static void parts_float_to_ahp(FloatParts64 *a, float_status *s)
{
switch (a->cls) {
- case float_class_qnan:
case float_class_snan:
+ float_raise(float_flag_invalid_snan, s);
+ /* fall through */
+ case float_class_qnan:
/*
* There is no NaN in the destination format. Raise Invalid
* and return a zero with the sign of the input NaN.
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index ce580347dd..db3e1f393d 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -19,7 +19,7 @@ static void partsN(return_nan)(FloatPartsN *a, float_status
*s)
{
switch (a->cls) {
case float_class_snan:
- float_raise(float_flag_invalid, s);
+ float_raise(float_flag_invalid | float_flag_invalid_snan, s);
if (s->default_nan_mode) {
parts_default_nan(a, s);
} else {
@@ -40,7 +40,7 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a,
FloatPartsN *b,
float_status *s)
{
if (is_snan(a->cls) || is_snan(b->cls)) {
- float_raise(float_flag_invalid, s);
+ float_raise(float_flag_invalid | float_flag_invalid_snan, s);
}
if (s->default_nan_mode) {
@@ -68,7 +68,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a,
FloatPartsN *b,
int which;
if (unlikely(abc_mask & float_cmask_snan)) {
- float_raise(float_flag_invalid, s);
+ float_raise(float_flag_invalid | float_flag_invalid_snan, s);
}
which = pickNaNMulAdd(a->cls, b->cls, c->cls,
@@ -1049,8 +1049,10 @@ static int64_t partsN(float_to_sint)(FloatPartsN *p,
FloatRoundMode rmode,
switch (p->cls) {
case float_class_snan:
+ flags |= float_flag_invalid_snan;
+ /* fall through */
case float_class_qnan:
- flags = float_flag_invalid;
+ flags |= float_flag_invalid;
r = max;
break;
@@ -1114,8 +1116,10 @@ static uint64_t partsN(float_to_uint)(FloatPartsN *p,
FloatRoundMode rmode,
switch (p->cls) {
case float_class_snan:
+ flags |= float_flag_invalid_snan;
+ /* fall through */
case float_class_qnan:
- flags = float_flag_invalid;
+ flags |= float_flag_invalid;
r = max;
break;
@@ -1341,7 +1345,9 @@ static FloatRelation partsN(compare)(FloatPartsN *a,
FloatPartsN *b,
}
if (unlikely(ab_mask & float_cmask_anynan)) {
- if (!is_quiet || (ab_mask & float_cmask_snan)) {
+ if (ab_mask & float_cmask_snan) {
+ float_raise(float_flag_invalid | float_flag_invalid_snan, s);
+ } else if (!is_quiet) {
float_raise(float_flag_invalid, s);
}
return float_relation_unordered;
--
2.25.1
- [RFC PATCH for-7.0 00/35] target/ppc fpu fixes and cleanups, Richard Henderson, 2021/11/19
- [PATCH 02/35] softfloat: Add flag specific to Inf - Inf, Richard Henderson, 2021/11/19
- [PATCH 03/35] softfloat: Add flag specific to Inf * 0, Richard Henderson, 2021/11/19
- [PATCH 06/35] softfloat: Add flag specific to convert non-nan to int, Richard Henderson, 2021/11/19
- [PATCH 08/35] target/ppc: Update float_invalid_op_addsub for new flags, Richard Henderson, 2021/11/19
- [PATCH 01/35] softfloat: Extend float_exception_flags to 16 bits, Richard Henderson, 2021/11/19
- [PATCH 04/35] softfloat: Add flags specific to Inf / Inf and 0 / 0, Richard Henderson, 2021/11/19
- [PATCH 05/35] softfloat: Add flag specific to sqrt(-x), Richard Henderson, 2021/11/19
- [PATCH 09/35] target/ppc: Update float_invalid_op_mul for new flags, Richard Henderson, 2021/11/19
- [PATCH 07/35] softfloat: Add flag specific to signaling nans,
Richard Henderson <=
- [PATCH 10/35] target/ppc: Update float_invalid_op_div for new flags, Richard Henderson, 2021/11/19
- [PATCH 11/35] target/ppc: Move float_check_status from FPU_FCTI to translate, Richard Henderson, 2021/11/19
- [PATCH 12/35] target/ppc: Update float_invalid_cvt for new flags, Richard Henderson, 2021/11/19
- [PATCH 14/35] target/ppc: Remove inline from do_fri, Richard Henderson, 2021/11/19
- [PATCH 13/35] target/ppc: Fix VXCVI return value, Richard Henderson, 2021/11/19
- [PATCH 19/35] target/ppc: Split out do_fmadd, Richard Henderson, 2021/11/19
- [PATCH 15/35] target/ppc: Use FloatRoundMode in do_fri, Richard Henderson, 2021/11/19
- [PATCH 16/35] target/ppc: Tidy inexact handling in do_fri, Richard Henderson, 2021/11/19
- [PATCH 17/35] target/ppc: Clean up do_fri, Richard Henderson, 2021/11/19
- [PATCH 18/35] target/ppc: Update fmadd for new flags, Richard Henderson, 2021/11/19