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[PATCH 11/35] target/ppc: Move float_check_status from FPU_FCTI to trans
From: |
Richard Henderson |
Subject: |
[PATCH 11/35] target/ppc: Move float_check_status from FPU_FCTI to translate |
Date: |
Fri, 19 Nov 2021 17:04:38 +0100 |
Fixes a bug in which e.g XE enabled causes inexact to be raised
before the writeback to the architectural register.
All of the users of GEN_FLOAT_B either set set_fprf, or are one
of the convert-to-integer instructions that require this behaviour.
Split out the two gen_helper_* calls in gen_compute_fprf_float64
and protect only the first with set_fprf.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/fpu_helper.c | 9 +++------
target/ppc/translate/fp-impl.c.inc | 3 ++-
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 2ab34236a3..0d58fd82a6 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -552,12 +552,9 @@ uint64_t helper_##op(CPUPPCState *env, float64 arg)
\
uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \
int status = get_float_exception_flags(&env->fp_status); \
\
- if (unlikely(status)) { \
- if (status & float_flag_invalid) { \
- float_invalid_cvt(env, 1, GETPC(), float64_classify(arg)); \
- ret = nanval; \
- } \
- do_float_check_status(env, GETPC()); \
+ if (unlikely(status & float_flag_invalid)) { \
+ float_invalid_cvt(env, 1, GETPC(), float64_classify(arg)); \
+ ret = nanval; \
} \
return ret; \
}
diff --git a/target/ppc/translate/fp-impl.c.inc
b/target/ppc/translate/fp-impl.c.inc
index c9e05201d9..aad97a12e8 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -157,8 +157,9 @@ static void gen_f##name(DisasContext *ctx)
\
gen_helper_f##name(t1, cpu_env, t0); \
set_fpr(rD(ctx->opcode), t1); \
if (set_fprf) { \
- gen_compute_fprf_float64(t1); \
+ gen_helper_compute_fprf_float64(cpu_env, t1); \
} \
+ gen_helper_float_check_status(cpu_env); \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
--
2.25.1
- [PATCH 02/35] softfloat: Add flag specific to Inf - Inf, (continued)
- [PATCH 02/35] softfloat: Add flag specific to Inf - Inf, Richard Henderson, 2021/11/19
- [PATCH 03/35] softfloat: Add flag specific to Inf * 0, Richard Henderson, 2021/11/19
- [PATCH 06/35] softfloat: Add flag specific to convert non-nan to int, Richard Henderson, 2021/11/19
- [PATCH 08/35] target/ppc: Update float_invalid_op_addsub for new flags, Richard Henderson, 2021/11/19
- [PATCH 01/35] softfloat: Extend float_exception_flags to 16 bits, Richard Henderson, 2021/11/19
- [PATCH 04/35] softfloat: Add flags specific to Inf / Inf and 0 / 0, Richard Henderson, 2021/11/19
- [PATCH 05/35] softfloat: Add flag specific to sqrt(-x), Richard Henderson, 2021/11/19
- [PATCH 09/35] target/ppc: Update float_invalid_op_mul for new flags, Richard Henderson, 2021/11/19
- [PATCH 07/35] softfloat: Add flag specific to signaling nans, Richard Henderson, 2021/11/19
- [PATCH 10/35] target/ppc: Update float_invalid_op_div for new flags, Richard Henderson, 2021/11/19
- [PATCH 11/35] target/ppc: Move float_check_status from FPU_FCTI to translate,
Richard Henderson <=
- [PATCH 12/35] target/ppc: Update float_invalid_cvt for new flags, Richard Henderson, 2021/11/19
- [PATCH 14/35] target/ppc: Remove inline from do_fri, Richard Henderson, 2021/11/19
- [PATCH 13/35] target/ppc: Fix VXCVI return value, Richard Henderson, 2021/11/19
- [PATCH 19/35] target/ppc: Split out do_fmadd, Richard Henderson, 2021/11/19
- [PATCH 15/35] target/ppc: Use FloatRoundMode in do_fri, Richard Henderson, 2021/11/19
- [PATCH 16/35] target/ppc: Tidy inexact handling in do_fri, Richard Henderson, 2021/11/19
- [PATCH 17/35] target/ppc: Clean up do_fri, Richard Henderson, 2021/11/19
- [PATCH 18/35] target/ppc: Update fmadd for new flags, Richard Henderson, 2021/11/19
- [PATCH 20/35] target/ppc: Do not call do_float_check_status from do_fmadd, Richard Henderson, 2021/11/19
- [PATCH 21/35] target/ppc: Split out do_frsp, Richard Henderson, 2021/11/19