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[PATCH v5 15/22] target/riscv: Fix RESERVED field length in VTYPE
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From: |
LIU Zhiwei |
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Subject: |
[PATCH v5 15/22] target/riscv: Fix RESERVED field length in VTYPE |
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Date: |
Thu, 25 Nov 2021 15:39:44 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1e56405243..2cee98f152 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -105,7 +105,7 @@ typedef struct CPURISCVState CPURISCVState;
FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
FIELD(VTYPE, VEDIV, 5, 2)
-FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
+FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8)
FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
--
2.25.1
- [PATCH v5 06/22] target/riscv: Extend pc for runtime pc write, (continued)
- [PATCH v5 06/22] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 2021/11/25
- [PATCH v5 07/22] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2021/11/25
- [PATCH v5 08/22] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2021/11/25
- [PATCH v5 09/22] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 10/22] target/riscv: Create current pm fields in env, LIU Zhiwei, 2021/11/25
- [PATCH v5 11/22] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2021/11/25
- [PATCH v5 12/22] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 13/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2021/11/25
- [PATCH v5 14/22] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/25
- [PATCH v5 15/22] target/riscv: Fix RESERVED field length in VTYPE,
LIU Zhiwei <=
- [PATCH v5 16/22] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 17/22] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2021/11/25
- [PATCH v5 18/22] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 19/22] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/25
- [PATCH v5 20/22] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2021/11/25
- [PATCH v5 21/22] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 22/22] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/25