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[PATCH v5 22/22] target/riscv: Enable uxl field write
From: |
LIU Zhiwei |
Subject: |
[PATCH v5 22/22] target/riscv: Enable uxl field write |
Date: |
Thu, 25 Nov 2021 15:39:51 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 2 ++
target/riscv/csr.c | 8 +++++---
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 9913fa9f77..5106f0e769 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -413,6 +413,8 @@ typedef enum {
#define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */
#define SSTATUS_MXR 0x00080000
+#define SSTATUS64_UXL 0x0000000300000000ULL
+
#define SSTATUS32_SD 0x80000000
#define SSTATUS64_SD 0x8000000000000000ULL
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3f284090fc..735d9a7825 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -553,15 +553,14 @@ static RISCVException write_mstatus(CPURISCVState *env,
int csrno,
* RV32: MPV and GVA are not in mstatus. The current plan is to
* add them to mstatush. For now, we just don't support it.
*/
- mask |= MSTATUS_MPV | MSTATUS_GVA;
+ mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL;
}
mstatus = (mstatus & ~mask) | (val & mask);
if (riscv_cpu_mxl(env) == MXL_RV64) {
- /* SXL and UXL fields are for now read only */
+ /* SXL fields are for now read only */
mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
- mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
}
env->mstatus = mstatus;
env->xl = cpu_get_xl(env);
@@ -842,6 +841,9 @@ static RISCVException write_sstatus(CPURISCVState *env, int
csrno,
target_ulong val)
{
target_ulong mask = (sstatus_v1_10_mask);
+ if (env->xl != MXL_RV32) {
+ mask |= SSTATUS64_UXL;
+ }
target_ulong newval = (env->mstatus & ~mask) | (val & mask);
return write_mstatus(env, CSR_MSTATUS, newval);
}
--
2.25.1
- [PATCH v5 12/22] target/riscv: Calculate address according to XLEN, (continued)
- [PATCH v5 12/22] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 13/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2021/11/25
- [PATCH v5 14/22] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/25
- [PATCH v5 15/22] target/riscv: Fix RESERVED field length in VTYPE, LIU Zhiwei, 2021/11/25
- [PATCH v5 16/22] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 17/22] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2021/11/25
- [PATCH v5 18/22] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 19/22] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/25
- [PATCH v5 20/22] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2021/11/25
- [PATCH v5 21/22] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 22/22] target/riscv: Enable uxl field write,
LIU Zhiwei <=