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Re: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver
From: |
Richard Henderson |
Subject: |
Re: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver |
Date: |
Tue, 4 Jan 2022 15:01:34 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 |
On 1/4/22 7:51 AM, Konrad Schwarz wrote:
+++ b/target/riscv/csr32-op-gdbserver.h
...
+++ b/target/riscv/csr64-op-gdbserver.h
There is a *lot* of overlap between these two files.
Why not add this data to the main csr_ops array?
That would put all the info for each csr in one place.
+ [CSR_CYCLE] { .gdb_type = "uint64", .gdb_group = "user" },
I think you should be able to use "unsigned long" as a proxy for the native
register size.
+char const riscv_gdb_csr_types[] =
+#ifdef TARGET_RISCV32
...
+#elif defined TARGET_RISCV64
...
+# endif
+;
Ideally we shouldn't use ifdefs for this -- we should choose one or the other depending on
the startup env->misa_mxl_max. We are still using an ifdef for the main
riscv-*-virtual.xml, but that could be considered a bug to fix.
r~
- [PATCH v1 4/5] RISC-V: Typed CSRs in gdbserver, (continued)
- [PATCH v1 4/5] RISC-V: Typed CSRs in gdbserver, Konrad Schwarz, 2022/01/02
- Re: [PATCH v1 4/5] RISC-V: Typed CSRs in gdbserver, Ralf Ramsauer, 2022/01/03
- [PATCH v2 0/5] Improve RISC-V debugging support., Konrad Schwarz, 2022/01/04
- [PATCH v2 2/5] RISC-V: monitor's print register functionality, Konrad Schwarz, 2022/01/04
- [PATCH v2 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations, Konrad Schwarz, 2022/01/04
- Re: [PATCH v2 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations, Alistair Francis, 2022/01/04
- RE: [PATCH v2 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations, Schwarz, Konrad, 2022/01/05
- [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver, Konrad Schwarz, 2022/01/04
- Re: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver, Alistair Francis, 2022/01/04
- RE: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver, Schwarz, Konrad, 2022/01/05
- Re: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver,
Richard Henderson <=
- RE: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver, Schwarz, Konrad, 2022/01/05
- Re: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver, Richard Henderson, 2022/01/05
- Re: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver, Alex Bennée, 2022/01/05
- RE: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver, Schwarz, Konrad, 2022/01/05
- Re: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver, Alex Bennée, 2022/01/05
- [PATCH v2 5/5] RISC-V: Add `v' (virtualization mode) bit to the `priv' virtual debug register, Konrad Schwarz, 2022/01/04
- [PATCH v2 1/5] RISC-V: larger and more consistent register set for 'info registers', Konrad Schwarz, 2022/01/04
- Re: [PATCH v2 1/5] RISC-V: larger and more consistent register set for 'info registers', Richard Henderson, 2022/01/04
- RE: [PATCH v2 1/5] RISC-V: larger and more consistent register set for 'info registers', Schwarz, Konrad, 2022/01/05
- Re: [PATCH v2 1/5] RISC-V: larger and more consistent register set for 'info registers', Alex Bennée, 2022/01/05