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[PULL 03/37] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA re
From: |
Alistair Francis |
Subject: |
[PULL 03/37] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers |
Date: |
Sat, 8 Jan 2022 15:50:14 +1000 |
From: Jim Shu <jim.shu@sifive.com>
It's obvious that PDMA supports 64-bit access of 64-bit registers, and
in previous commit, we confirm that PDMA supports 32-bit access of
both 32/64-bit registers. Thus, we configure 32/64-bit memory access
of PDMA registers as valid in general.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20220104063408.658169-3-jim.shu@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/dma/sifive_pdma.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
index f4df16449b..1dd88f3479 100644
--- a/hw/dma/sifive_pdma.c
+++ b/hw/dma/sifive_pdma.c
@@ -444,6 +444,10 @@ static const MemoryRegionOps sifive_pdma_ops = {
.impl = {
.min_access_size = 4,
.max_access_size = 8,
+ },
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 8,
}
};
--
2.31.1
- [PULL 00/37] riscv-to-apply queue, Alistair Francis, 2022/01/08
- [PULL 01/37] target/riscv/pmp: fix no pmp illegal intrs, Alistair Francis, 2022/01/08
- [PULL 02/37] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register, Alistair Francis, 2022/01/08
- [PULL 07/37] hw/intc: sifive_plic: Cleanup remaining functions, Alistair Francis, 2022/01/08
- [PULL 04/37] hw/intc: sifive_plic: Add a reset function, Alistair Francis, 2022/01/08
- [PULL 05/37] hw/intc: sifive_plic: Cleanup the write function, Alistair Francis, 2022/01/08
- [PULL 03/37] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers,
Alistair Francis <=
- [PULL 08/37] target/riscv: Mark the Hypervisor extension as non experimental, Alistair Francis, 2022/01/08
- [PULL 10/37] hw/riscv: Use error_fatal for SoC realisation, Alistair Francis, 2022/01/08
- [PULL 06/37] hw/intc: sifive_plic: Cleanup the read function, Alistair Francis, 2022/01/08
- [PULL 09/37] target/riscv: Enable the Hypervisor extension by default, Alistair Francis, 2022/01/08
- [PULL 11/37] hw/riscv: virt: Allow support for 32 cores, Alistair Francis, 2022/01/08
- [PULL 12/37] roms/opensbi: Upgrade from v0.9 to v1.0, Alistair Francis, 2022/01/08
- [PULL 13/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp insns, Alistair Francis, 2022/01/08
- [PULL 14/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp/int type-convert insns, Alistair Francis, 2022/01/08
- [PULL 15/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing fp/int type-convert insns, Alistair Francis, 2022/01/08
- [PULL 16/37] target/riscv: Fix position of 'experimental' comment, Alistair Francis, 2022/01/08