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[PULL 14/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check funct
From: |
Alistair Francis |
Subject: |
[PULL 14/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp/int type-convert insns |
Date: |
Sat, 8 Jan 2022 15:50:25 +1000 |
From: Frank Chang <frank.chang@sifive.com>
vfwcvt.xu.f.v, vfwcvt.x.f.v, vfwcvt.rtz.xu.f.v and vfwcvt.rtz.x.f.v
convert single-width floating-point to double-width integer.
Therefore, should use require_rvf() to check whether RVF/RVD is enabled.
vfwcvt.f.xu.v, vfwcvt.f.x.v convert single-width integer to double-width
floating-point, and vfwcvt.f.f.v convert double-width floating-point to
single-width floating-point. Therefore, should use require_scale_rvf() to
check whether RVF/RVD is enabled.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220105022247.21131-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 34 ++++++++++++++++++-------
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 8d92243f2b..f1b44ccad2 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2613,16 +2613,27 @@ GEN_OPFV_CVT_TRANS(vfcvt_rtz_x_f_v, vfcvt_x_f_v,
RISCV_FRM_RTZ)
static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
{
return require_rvv(s) &&
- require_scale_rvf(s) &&
- (s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_ds(s, a->rd, a->rs2, a->vm);
}
-#define GEN_OPFV_WIDEN_TRANS(NAME, HELPER, FRM) \
+static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
+{
+ return opfv_widen_check(s, a) &&
+ require_rvf(s);
+}
+
+static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
+{
+ return opfv_widen_check(s, a) &&
+ require_scale_rvf(s) &&
+ (s->sew != MO_8);
+}
+
+#define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
- if (opfv_widen_check(s, a)) { \
+ if (CHECK(s, a)) { \
if (FRM != RISCV_FRM_DYN) { \
gen_set_rm(s, RISCV_FRM_DYN); \
} \
@@ -2649,12 +2660,17 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
return false; \
}
-GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v, vfwcvt_xu_f_v, RISCV_FRM_DYN)
-GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v, vfwcvt_x_f_v, RISCV_FRM_DYN)
-GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v, vfwcvt_f_f_v, RISCV_FRM_DYN)
+GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v, opxfv_widen_check, vfwcvt_xu_f_v,
+ RISCV_FRM_DYN)
+GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v, opxfv_widen_check, vfwcvt_x_f_v,
+ RISCV_FRM_DYN)
+GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v, opffv_widen_check, vfwcvt_f_f_v,
+ RISCV_FRM_DYN)
/* Reuse the helper functions from vfwcvt.xu.f.v and vfwcvt.x.f.v */
-GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_xu_f_v, vfwcvt_xu_f_v, RISCV_FRM_RTZ)
-GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_x_f_v, vfwcvt_x_f_v, RISCV_FRM_RTZ)
+GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_xu_f_v, opxfv_widen_check, vfwcvt_xu_f_v,
+ RISCV_FRM_RTZ)
+GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_x_f_v, opxfv_widen_check, vfwcvt_x_f_v,
+ RISCV_FRM_RTZ)
static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
{
--
2.31.1
- [PULL 04/37] hw/intc: sifive_plic: Add a reset function, (continued)
- [PULL 04/37] hw/intc: sifive_plic: Add a reset function, Alistair Francis, 2022/01/08
- [PULL 05/37] hw/intc: sifive_plic: Cleanup the write function, Alistair Francis, 2022/01/08
- [PULL 03/37] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers, Alistair Francis, 2022/01/08
- [PULL 08/37] target/riscv: Mark the Hypervisor extension as non experimental, Alistair Francis, 2022/01/08
- [PULL 10/37] hw/riscv: Use error_fatal for SoC realisation, Alistair Francis, 2022/01/08
- [PULL 06/37] hw/intc: sifive_plic: Cleanup the read function, Alistair Francis, 2022/01/08
- [PULL 09/37] target/riscv: Enable the Hypervisor extension by default, Alistair Francis, 2022/01/08
- [PULL 11/37] hw/riscv: virt: Allow support for 32 cores, Alistair Francis, 2022/01/08
- [PULL 12/37] roms/opensbi: Upgrade from v0.9 to v1.0, Alistair Francis, 2022/01/08
- [PULL 13/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp insns, Alistair Francis, 2022/01/08
- [PULL 14/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp/int type-convert insns,
Alistair Francis <=
- [PULL 15/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing fp/int type-convert insns, Alistair Francis, 2022/01/08
- [PULL 16/37] target/riscv: Fix position of 'experimental' comment, Alistair Francis, 2022/01/08
- [PULL 18/37] exec/memop: Adding signed quad and octo defines, Alistair Francis, 2022/01/08
- [PULL 17/37] exec/memop: Adding signedness to quad definitions, Alistair Francis, 2022/01/08
- [PULL 19/37] qemu/int128: addition of div/rem 128-bit operations, Alistair Francis, 2022/01/08
- [PULL 20/37] target/riscv: additional macros to check instruction support, Alistair Francis, 2022/01/08
- [PULL 21/37] target/riscv: separation of bitwise logic and arithmetic helpers, Alistair Francis, 2022/01/08
- [PULL 22/37] target/riscv: array for the 64 upper bits of 128-bit registers, Alistair Francis, 2022/01/08
- [PULL 23/37] target/riscv: setup everything for rv64 to support rv128 execution, Alistair Francis, 2022/01/08
- [PULL 25/37] target/riscv: accessors to registers upper part and 128-bit load/store, Alistair Francis, 2022/01/08