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Re: [PULL 00/61] riscv-to-apply queue
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From: |
Peter Maydell |
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Subject: |
Re: [PULL 00/61] riscv-to-apply queue |
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Date: |
Fri, 21 Jan 2022 12:58:01 +0000 |
On Fri, 21 Jan 2022 at 06:11, Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit 2c89b5af5e72ab8c9d544c6e30399528b2238827:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20220120-1' into staging (2022-01-20
> 16:13:17 +0000)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220121-1
>
> for you to fetch changes up to f297245f6a780f496fb171af6fcd21ff3e6783c3:
>
> target/riscv: Relax UXL field for debugging (2022-01-21 15:52:57 +1000)
>
> ----------------------------------------------------------------
> Third RISC-V PR for QEMU 7.0
>
> * Fixes for OpenTitan timer
> * Correction of OpenTitan PLIC stride length
> * RISC-V KVM support
> * Device tree code cleanup
> * Support for the Zve64f and Zve32f extensions
> * OpenSBI binary loading support for the Spike machine
> * Removal of OpenSBI ELFs
> * Support for the UXL field in xstatus
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.
-- PMM
- [PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN, (continued)
- [PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN, Alistair Francis, 2022/01/21
- [PULL 46/61] target/riscv: Use gdb xml according to max mxlen, Alistair Francis, 2022/01/21
- [PULL 47/61] target/riscv: Relax debug check for pm write, Alistair Francis, 2022/01/21
- [PULL 56/61] target/riscv: Fix check range for first fault only, Alistair Francis, 2022/01/21
- [PULL 57/61] target/riscv: Adjust vector address with mask, Alistair Francis, 2022/01/21
- [PULL 59/61] target/riscv: Set default XLEN for hypervisor, Alistair Francis, 2022/01/21
- [PULL 61/61] target/riscv: Relax UXL field for debugging, Alistair Francis, 2022/01/21
- [PULL 60/61] target/riscv: Enable uxl field write, Alistair Francis, 2022/01/21
- [PULL 53/61] target/riscv: Split out the vill from vtype, Alistair Francis, 2022/01/21
- [PULL 48/61] target/riscv: Adjust csr write mask with XLEN, Alistair Francis, 2022/01/21
- Re: [PULL 00/61] riscv-to-apply queue,
Peter Maydell <=