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[PULL 56/61] target/riscv: Fix check range for first fault only
From: |
Alistair Francis |
Subject: |
[PULL 56/61] target/riscv: Fix check range for first fault only |
Date: |
Fri, 21 Jan 2022 15:58:25 +1000 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Only check the range that has passed the address translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-19-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8b7c9ec890..efb3129532 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -500,12 +500,12 @@ vext_ldff(void *vd, void *v0, target_ulong base,
cpu_mmu_index(env, false));
if (host) {
#ifdef CONFIG_USER_ONLY
- if (page_check_range(addr, nf << esz, PAGE_READ) < 0) {
+ if (page_check_range(addr, offset, PAGE_READ) < 0) {
vl = i;
goto ProbeSuccess;
}
#else
- probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
+ probe_pages(env, addr, offset, ra, MMU_DATA_LOAD);
#endif
} else {
vl = i;
--
2.31.1
- [PULL 41/61] target/riscv: Sign extend link reg for jal and jalr, (continued)
- [PULL 41/61] target/riscv: Sign extend link reg for jal and jalr, Alistair Francis, 2022/01/21
- [PULL 43/61] target/riscv: Create xl field in env, Alistair Francis, 2022/01/21
- [PULL 42/61] target/riscv: Sign extend pc for different XLEN, Alistair Francis, 2022/01/21
- [PULL 44/61] target/riscv: Ignore the pc bits above XLEN, Alistair Francis, 2022/01/21
- [PULL 45/61] target/riscv: Extend pc for runtime pc write, Alistair Francis, 2022/01/21
- [PULL 54/61] target/riscv: Adjust vsetvl according to XLEN, Alistair Francis, 2022/01/21
- [PULL 55/61] target/riscv: Remove VILL field in VTYPE, Alistair Francis, 2022/01/21
- [PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN, Alistair Francis, 2022/01/21
- [PULL 46/61] target/riscv: Use gdb xml according to max mxlen, Alistair Francis, 2022/01/21
- [PULL 47/61] target/riscv: Relax debug check for pm write, Alistair Francis, 2022/01/21
- [PULL 56/61] target/riscv: Fix check range for first fault only,
Alistair Francis <=
- [PULL 57/61] target/riscv: Adjust vector address with mask, Alistair Francis, 2022/01/21
- [PULL 59/61] target/riscv: Set default XLEN for hypervisor, Alistair Francis, 2022/01/21
- [PULL 61/61] target/riscv: Relax UXL field for debugging, Alistair Francis, 2022/01/21
- [PULL 60/61] target/riscv: Enable uxl field write, Alistair Francis, 2022/01/21
- [PULL 53/61] target/riscv: Split out the vill from vtype, Alistair Francis, 2022/01/21
- [PULL 48/61] target/riscv: Adjust csr write mask with XLEN, Alistair Francis, 2022/01/21
- Re: [PULL 00/61] riscv-to-apply queue, Peter Maydell, 2022/01/21