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[PATCH v3 2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-t
From: |
Philipp Tomsich |
Subject: |
[PATCH v3 2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr |
Date: |
Fri, 28 Jan 2022 15:56:37 +0100 |
As the number of extensions is growing, copying them individiually
into the DisasContext will scale less and less... instead we populate
a pointer to the RISCVCPUConfig structure in the DisasContext.
This adds an extra indirection when checking for the availability of
an extension (compared to copying the fields into DisasContext).
While not a performance problem today, we can always (shallow) copy
the entire structure into the DisasContext (instead of putting a
pointer to it) if this is ever deemed necessary.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
---
Changes in v3:
- (new patch) copy pointer to element cfg into DisasContext
target/riscv/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f0bbe80875..22d09af2df 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -76,6 +76,7 @@ typedef struct DisasContext {
int frm;
RISCVMXL ol;
bool virt_enabled;
+ const struct RISCVCPUConfig *cfg_ptr;
bool ext_ifencei;
bool ext_zfh;
bool ext_zfhmin;
@@ -908,6 +909,7 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
#endif
ctx->misa_ext = env->misa_ext;
ctx->frm = -1; /* unknown rounding mode */
+ ctx->cfg_ptr = &(cpu->cfg);
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
ctx->ext_zfh = cpu->cfg.ext_zfh;
ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
--
2.33.1
- [PATCH v3 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes, Philipp Tomsich, 2022/01/28
- [PATCH v3 1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig', Philipp Tomsich, 2022/01/28
- [PATCH v3 2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr,
Philipp Tomsich <=
- [PATCH v3 4/7] target/riscv: access cfg structure through DisasContext, Philipp Tomsich, 2022/01/28
- [PATCH v3 3/7] target/riscv: access configuration through cfg_ptr in DisasContext, Philipp Tomsich, 2022/01/28
- [PATCH v3 7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps, Philipp Tomsich, 2022/01/28
- [PATCH v3 6/7] target/riscv: Add XVentanaCondOps custom extension, Philipp Tomsich, 2022/01/28
- [PATCH v3 5/7] target/riscv: iterate over a table of decoders, Philipp Tomsich, 2022/01/28