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[PULL 19/32] hw/intc/arm_gicv3: Initialise dma_as in GIC, not ITS
From: |
Peter Maydell |
Subject: |
[PULL 19/32] hw/intc/arm_gicv3: Initialise dma_as in GIC, not ITS |
Date: |
Fri, 28 Jan 2022 15:29:56 +0000 |
In our implementation, all ITSes connected to a GIC share a single
AddressSpace, which we keep in the GICv3State::dma_as field and
initialized based on the GIC's 'sysmem' property. The right place
to set it up by calling address_space_init() is therefore in the
GIC's realize method, not the ITS's realize.
This fixes a theoretical bug where QEMU hangs on startup if the board
model creates two ITSes connected to the same GIC -- we would call
address_space_init() twice on the same AddressSpace*, which creates
an infinite loop in the QTAILQ that softmmu/memory.c uses to store
its list of AddressSpaces and causes any subsequent attempt to
iterate through that list to loop forever. There aren't any board
models like that in the tree at the moment, though.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-4-peter.maydell@linaro.org
---
hw/intc/arm_gicv3_common.c | 5 +++++
hw/intc/arm_gicv3_its.c | 3 ---
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 9884d2e39b9..579aa0cb9ed 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -357,6 +357,11 @@ static void arm_gicv3_common_realize(DeviceState *dev,
Error **errp)
return;
}
+ if (s->lpi_enable) {
+ address_space_init(&s->dma_as, s->dma,
+ "gicv3-its-sysmem");
+ }
+
s->cpu = g_new0(GICv3CPUState, s->num_cpu);
for (i = 0; i < s->num_cpu; i++) {
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index 6d2549e64b1..67f12d98af3 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -1194,9 +1194,6 @@ static void gicv3_arm_its_realize(DeviceState *dev, Error
**errp)
gicv3_its_init_mmio(s, &gicv3_its_control_ops, &gicv3_its_translation_ops);
- address_space_init(&s->gicv3->dma_as, s->gicv3->dma,
- "gicv3-its-sysmem");
-
/* set the ITS default features supported */
s->typer = FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL, 1);
s->typer = FIELD_DP64(s->typer, GITS_TYPER, ITT_ENTRY_SIZE,
--
2.25.1
- [PULL 31/32] hw/arm: ast2600: Fix address mapping of second SPI controller, (continued)
- [PULL 31/32] hw/arm: ast2600: Fix address mapping of second SPI controller, Peter Maydell, 2022/01/28
- [PULL 15/32] MAINTAINERS: Remove myself (for raspi)., Peter Maydell, 2022/01/28
- [PULL 11/32] hw/arm/xlnx-versal: Connect the OSPI flash memory controller model, Peter Maydell, 2022/01/28
- [PULL 20/32] hw/intc/arm_gicv3_its: Don't clear GITS_CREADR when GITS_CTLR.ENABLED is set, Peter Maydell, 2022/01/28
- [PULL 26/32] hw/intc/arm_gicv3_its: Provide read accessor for translation_ops, Peter Maydell, 2022/01/28
- [PULL 03/32] hw/char/exynos4210_uart: Fix crash on trying to load VM state, Peter Maydell, 2022/01/28
- [PULL 21/32] hw/intc/arm_gicv3_its: Don't clear GITS_CWRITER on writes to GITS_CBASER, Peter Maydell, 2022/01/28
- [PULL 08/32] include/hw/dma/xlnx_csu_dma: Add in missing includes in the header, Peter Maydell, 2022/01/28
- [PULL 18/32] hw/intc/arm_gicv3_its: Add tracepoints, Peter Maydell, 2022/01/28
- [PULL 22/32] hw/intc/arm_gicv3: Honour GICD_CTLR.EnableGrp1NS for LPIs, Peter Maydell, 2022/01/28
- [PULL 19/32] hw/intc/arm_gicv3: Initialise dma_as in GIC, not ITS,
Peter Maydell <=
- [PULL 32/32] target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp, Peter Maydell, 2022/01/28
- [PULL 30/32] hw/intc/arm_gicv3_its: Implement MOVI, Peter Maydell, 2022/01/28
- [PULL 28/32] hw/intc/arm_gicv3_its: Check table bounds against correct limit, Peter Maydell, 2022/01/28
- [PULL 02/32] hw/armv7m: Fix broken VMStateDescription, Peter Maydell, 2022/01/28
- [PULL 05/32] hw/misc: Add a model of Versal's PMC SLCR, Peter Maydell, 2022/01/28
- [PULL 29/32] hw/intc/arm_gicv3_its: Implement MOVALL, Peter Maydell, 2022/01/28
- [PULL 24/32] hw/intc/arm_gicv3_redist: Remove unnecessary zero checks, Peter Maydell, 2022/01/28
- [PULL 09/32] hw/dma/xlnx_csu_dma: Support starting a read transfer through a class method, Peter Maydell, 2022/01/28
- [PULL 27/32] hw/intc/arm_gicv3_its: Make GITS_BASER<n> RAZ/WI for unimplemented registers, Peter Maydell, 2022/01/28
- [PULL 12/32] hw/block/m25p80: Add support for Micron Xccela flash mt35xu01g, Peter Maydell, 2022/01/28