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[PULL 11/32] hw/arm/xlnx-versal: Connect the OSPI flash memory controlle
From: |
Peter Maydell |
Subject: |
[PULL 11/32] hw/arm/xlnx-versal: Connect the OSPI flash memory controller model |
Date: |
Fri, 28 Jan 2022 15:29:48 +0000 |
From: Francisco Iglesias <francisco.iglesias@xilinx.com>
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220121161141.14389-8-francisco.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/xlnx-versal.h | 20 ++++++++
hw/arm/xlnx-versal.c | 93 ++++++++++++++++++++++++++++++++++++
2 files changed, 113 insertions(+)
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 811df73350b..1b5ad4de802 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -26,6 +26,8 @@
#include "hw/misc/xlnx-versal-xramc.h"
#include "hw/nvram/xlnx-bbram.h"
#include "hw/nvram/xlnx-versal-efuse.h"
+#include "hw/ssi/xlnx-versal-ospi.h"
+#include "hw/dma/xlnx_csu_dma.h"
#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
@@ -80,6 +82,14 @@ struct Versal {
struct {
SDHCIState sd[XLNX_VERSAL_NR_SDS];
XlnxVersalPmcIouSlcr slcr;
+
+ struct {
+ XlnxVersalOspi ospi;
+ XlnxCSUDMA dma_src;
+ XlnxCSUDMA dma_dst;
+ MemoryRegion linear_mr;
+ qemu_or_irq irq_orgate;
+ } ospi;
} iou;
XlnxZynqMPRTC rtc;
@@ -116,6 +126,7 @@ struct Versal {
#define VERSAL_ADMA_IRQ_0 60
#define VERSAL_XRAM_IRQ_0 79
#define VERSAL_PMC_APB_IRQ 121
+#define VERSAL_OSPI_IRQ 124
#define VERSAL_SD0_IRQ_0 126
#define VERSAL_EFUSE_IRQ 139
#define VERSAL_RTC_ALARM_IRQ 142
@@ -184,6 +195,15 @@ struct Versal {
#define MM_PMC_PMC_IOU_SLCR 0xf1060000
#define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000
+#define MM_PMC_OSPI 0xf1010000
+#define MM_PMC_OSPI_SIZE 0x10000
+
+#define MM_PMC_OSPI_DAC 0xc0000000
+#define MM_PMC_OSPI_DAC_SIZE 0x20000000
+
+#define MM_PMC_OSPI_DMA_DST 0xf1011800
+#define MM_PMC_OSPI_DMA_SRC 0xf1011000
+
#define MM_PMC_SD0 0xf1040000U
#define MM_PMC_SD0_SIZE 0x10000
#define MM_PMC_BBRAM_CTRL 0xf11f0000
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index c8c0c102c74..ab58bebfd2e 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -28,6 +28,7 @@
#define GEM_REVISION 0x40070106
#define VERSAL_NUM_PMC_APB_IRQS 3
+#define NUM_OSPI_IRQ_LINES 3
static void versal_create_apu_cpus(Versal *s)
{
@@ -412,6 +413,97 @@ static void versal_create_pmc_iou_slcr(Versal *s, qemu_irq
*pic)
qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 2));
}
+static void versal_create_ospi(Versal *s, qemu_irq *pic)
+{
+ SysBusDevice *sbd;
+ MemoryRegion *mr_dac;
+ qemu_irq ospi_mux_sel;
+ DeviceState *orgate;
+
+ memory_region_init(&s->pmc.iou.ospi.linear_mr, OBJECT(s),
+ "versal-ospi-linear-mr" , MM_PMC_OSPI_DAC_SIZE);
+
+ object_initialize_child(OBJECT(s), "versal-ospi", &s->pmc.iou.ospi.ospi,
+ TYPE_XILINX_VERSAL_OSPI);
+
+ mr_dac = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 1);
+ memory_region_add_subregion(&s->pmc.iou.ospi.linear_mr, 0x0, mr_dac);
+
+ /* Create the OSPI destination DMA */
+ object_initialize_child(OBJECT(s), "versal-ospi-dma-dst",
+ &s->pmc.iou.ospi.dma_dst,
+ TYPE_XLNX_CSU_DMA);
+
+ object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_dst),
+ "dma", OBJECT(get_system_memory()),
+ &error_abort);
+
+ sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst);
+ sysbus_realize(sbd, &error_fatal);
+
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_DST,
+ sysbus_mmio_get_region(sbd, 0));
+
+ /* Create the OSPI source DMA */
+ object_initialize_child(OBJECT(s), "versal-ospi-dma-src",
+ &s->pmc.iou.ospi.dma_src,
+ TYPE_XLNX_CSU_DMA);
+
+ object_property_set_bool(OBJECT(&s->pmc.iou.ospi.dma_src), "is-dst",
+ false, &error_abort);
+
+ object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src),
+ "dma", OBJECT(mr_dac), &error_abort);
+
+ object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src),
+ "stream-connected-dma",
+ OBJECT(&s->pmc.iou.ospi.dma_dst),
+ &error_abort);
+
+ sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src);
+ sysbus_realize(sbd, &error_fatal);
+
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_SRC,
+ sysbus_mmio_get_region(sbd, 0));
+
+ /* Realize the OSPI */
+ object_property_set_link(OBJECT(&s->pmc.iou.ospi.ospi), "dma-src",
+ OBJECT(&s->pmc.iou.ospi.dma_src), &error_abort);
+
+ sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi);
+ sysbus_realize(sbd, &error_fatal);
+
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI,
+ sysbus_mmio_get_region(sbd, 0));
+
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DAC,
+ &s->pmc.iou.ospi.linear_mr);
+
+ /* ospi_mux_sel */
+ ospi_mux_sel = qdev_get_gpio_in_named(DEVICE(&s->pmc.iou.ospi.ospi),
+ "ospi-mux-sel", 0);
+ qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "ospi-mux-sel", 0,
+ ospi_mux_sel);
+
+ /* OSPI irq */
+ object_initialize_child(OBJECT(s), "ospi-irq-orgate",
+ &s->pmc.iou.ospi.irq_orgate, TYPE_OR_IRQ);
+ object_property_set_int(OBJECT(&s->pmc.iou.ospi.irq_orgate),
+ "num-lines", NUM_OSPI_IRQ_LINES, &error_fatal);
+
+ orgate = DEVICE(&s->pmc.iou.ospi.irq_orgate);
+ qdev_realize(orgate, NULL, &error_fatal);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 0,
+ qdev_get_gpio_in(orgate, 0));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src), 0,
+ qdev_get_gpio_in(orgate, 1));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst), 0,
+ qdev_get_gpio_in(orgate, 2));
+
+ qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]);
+}
+
/* This takes the board allocated linear DDR memory and creates aliases
* for each split DDR range/aperture on the Versal address map.
*/
@@ -552,6 +644,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
versal_create_bbram(s, pic);
versal_create_efuse(s, pic);
versal_create_pmc_iou_slcr(s, pic);
+ versal_create_ospi(s, pic);
versal_map_ddr(s);
versal_unimp(s);
--
2.25.1
- [PULL 17/32] target/arm: Log CPU index in 'Taking exception' log, (continued)
- [PULL 17/32] target/arm: Log CPU index in 'Taking exception' log, Peter Maydell, 2022/01/28
- [PULL 04/32] rtc: Move RTC function prototypes to their own header, Peter Maydell, 2022/01/28
- [PULL 07/32] hw/arm/xlnx-versal: Connect Versal's PMC SLCR, Peter Maydell, 2022/01/28
- [PULL 23/32] hw/intc/arm_gicv3_its: Sort ITS command list into numeric order, Peter Maydell, 2022/01/28
- [PULL 25/32] hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supported, Peter Maydell, 2022/01/28
- [PULL 14/32] MAINTAINERS: Add an entry for Xilinx Versal OSPI, Peter Maydell, 2022/01/28
- [PULL 10/32] hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller, Peter Maydell, 2022/01/28
- [PULL 13/32] hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI, Peter Maydell, 2022/01/28
- [PULL 31/32] hw/arm: ast2600: Fix address mapping of second SPI controller, Peter Maydell, 2022/01/28
- [PULL 15/32] MAINTAINERS: Remove myself (for raspi)., Peter Maydell, 2022/01/28
- [PULL 11/32] hw/arm/xlnx-versal: Connect the OSPI flash memory controller model,
Peter Maydell <=
- [PULL 20/32] hw/intc/arm_gicv3_its: Don't clear GITS_CREADR when GITS_CTLR.ENABLED is set, Peter Maydell, 2022/01/28
- [PULL 26/32] hw/intc/arm_gicv3_its: Provide read accessor for translation_ops, Peter Maydell, 2022/01/28
- [PULL 03/32] hw/char/exynos4210_uart: Fix crash on trying to load VM state, Peter Maydell, 2022/01/28
- [PULL 21/32] hw/intc/arm_gicv3_its: Don't clear GITS_CWRITER on writes to GITS_CBASER, Peter Maydell, 2022/01/28
- [PULL 08/32] include/hw/dma/xlnx_csu_dma: Add in missing includes in the header, Peter Maydell, 2022/01/28
- [PULL 18/32] hw/intc/arm_gicv3_its: Add tracepoints, Peter Maydell, 2022/01/28
- [PULL 22/32] hw/intc/arm_gicv3: Honour GICD_CTLR.EnableGrp1NS for LPIs, Peter Maydell, 2022/01/28
- [PULL 19/32] hw/intc/arm_gicv3: Initialise dma_as in GIC, not ITS, Peter Maydell, 2022/01/28
- [PULL 32/32] target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp, Peter Maydell, 2022/01/28
- [PULL 30/32] hw/intc/arm_gicv3_its: Implement MOVI, Peter Maydell, 2022/01/28