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[PATCH v4 5/7] target/riscv: iterate over a table of decoders
From: |
Philipp Tomsich |
Subject: |
[PATCH v4 5/7] target/riscv: iterate over a table of decoders |
Date: |
Mon, 31 Jan 2022 00:57:57 +0100 |
To split up the decoder into multiple functions (both to support
vendor-specific opcodes in separate files and to simplify maintenance
of orthogonal extensions), this changes decode_op to iterate over a
table of decoders predicated on guard functions.
This commit only adds the new structure and the table, allowing for
the easy addition of additional decoders in the future.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
Changes in v4:
- add braces to comply with coding standard (as suggested by Richard)
- merge the two if-statements to reduce clutter after (now that the
braces have been added)
Changes in v3:
- expose only the DisasContext* to predicate functions
- mark the table of decoder functions as static
- drop the inline from always_true_p, until the need arises (i.e.,
someone finds a use for it and calls it directly)
- rewrite to drop the 'handled' temporary in iterating over the
decoder table, removing the assignment in the condition of the if
Changes in v2:
- (new patch) iterate over a table of guarded decoder functions
target/riscv/translate.c | 32 +++++++++++++++++++++++++++-----
1 file changed, 27 insertions(+), 5 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 441690846c..2742c32f1c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -111,6 +111,11 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
return ctx->misa_ext & ext;
}
+static bool always_true_p(DisasContext *ctx __attribute__((__unused__)))
+{
+ return true;
+}
+
#ifdef TARGET_RISCV32
#define get_xl(ctx) MXL_RV32
#elif defined(CONFIG_USER_ONLY)
@@ -855,15 +860,26 @@ static uint32_t opcode_at(DisasContextBase *dcbase,
target_ulong pc)
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
{
- /* check for compressed insn */
+ /*
+ * A table with predicate (i.e., guard) functions and decoder functions
+ * that are tested in-order until a decoder matches onto the opcode.
+ */
+ static const struct {
+ bool (*guard_func)(DisasContext *);
+ bool (*decode_func)(DisasContext *, uint32_t);
+ } decoders[] = {
+ { always_true_p, decode_insn32 },
+ };
+
+ /* Check for compressed insn */
if (extract16(opcode, 0, 2) != 3) {
if (!has_ext(ctx, RVC)) {
gen_exception_illegal(ctx);
} else {
ctx->opcode = opcode;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
- if (!decode_insn16(ctx, opcode)) {
- gen_exception_illegal(ctx);
+ if (decode_insn16(ctx, opcode)) {
+ return;
}
}
} else {
@@ -873,10 +889,16 @@ static void decode_opc(CPURISCVState *env, DisasContext
*ctx, uint16_t opcode)
ctx->base.pc_next + 2));
ctx->opcode = opcode32;
ctx->pc_succ_insn = ctx->base.pc_next + 4;
- if (!decode_insn32(ctx, opcode32)) {
- gen_exception_illegal(ctx);
+
+ for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
+ if (decoders[i].guard_func(ctx) &&
+ decoders[i].decode_func(ctx, opcode32)) {
+ return;
+ }
}
}
+
+ gen_exception_illegal(ctx);
}
static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
--
2.33.1
- [PATCH v4 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes, Philipp Tomsich, 2022/01/30
- [PATCH v4 4/7] target/riscv: access cfg structure through DisasContext, Philipp Tomsich, 2022/01/30
- [PATCH v4 2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr, Philipp Tomsich, 2022/01/30
- [PATCH v4 3/7] target/riscv: access configuration through cfg_ptr in DisasContext, Philipp Tomsich, 2022/01/30
- [PATCH v4 5/7] target/riscv: iterate over a table of decoders,
Philipp Tomsich <=
- [PATCH v4 6/7] target/riscv: Add XVentanaCondOps custom extension, Philipp Tomsich, 2022/01/30
- [PATCH v4 1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig', Philipp Tomsich, 2022/01/30
- [PATCH v4 7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps, Philipp Tomsich, 2022/01/30
- Re: [PATCH v4 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes, Richard Henderson, 2022/01/31