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[PATCH v6 21/43] hw/cxl/device: Plumb real Label Storage Area (LSA) sizi
From: |
Jonathan Cameron |
Subject: |
[PATCH v6 21/43] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing |
Date: |
Fri, 11 Feb 2022 12:07:25 +0000 |
From: Ben Widawsky <ben.widawsky@intel.com>
This should introduce no change. Subsequent work will make use of this
new class member.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/cxl/cxl-mailbox-utils.c | 3 +++
hw/mem/cxl_type3.c | 24 +++++++++---------------
include/hw/cxl/cxl_device.h | 29 +++++++++++++++++++++++++++++
3 files changed, 41 insertions(+), 15 deletions(-)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index d022711b2a..ccf9c3d794 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -278,6 +278,8 @@ static ret_code cmd_identify_memory_device(struct cxl_cmd
*cmd,
} __attribute__((packed)) *id;
_Static_assert(sizeof(*id) == 0x43, "Bad identify size");
+ CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
+ CXLType3Class *cvc = CXL_TYPE3_DEV_GET_CLASS(ct3d);
uint64_t size = cxl_dstate->pmem_size;
if (!QEMU_IS_ALIGNED(size, 256 << 20)) {
@@ -292,6 +294,7 @@ static ret_code cmd_identify_memory_device(struct cxl_cmd
*cmd,
id->total_capacity = size / (256 << 20);
id->persistent_capacity = size / (256 << 20);
+ id->lsa_size = cvc->get_lsa_size(ct3d);
*len = sizeof(*id);
return CXL_MBOX_SUCCESS;
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index da091157f2..b16262d3cc 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -13,21 +13,6 @@
#include "sysemu/hostmem.h"
#include "hw/cxl/cxl.h"
-typedef struct cxl_type3_dev {
- /* Private */
- PCIDevice parent_obj;
-
- /* Properties */
- uint64_t size;
- HostMemoryBackend *hostmem;
-
- /* State */
- CXLComponentState cxl_cstate;
- CXLDeviceState cxl_dstate;
-} CXLType3Dev;
-
-#define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV)
-
static void build_dvsecs(CXLType3Dev *ct3d)
{
CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
@@ -186,10 +171,16 @@ static Property ct3_props[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static uint64_t get_lsa_size(CXLType3Dev *ct3d)
+{
+ return 0;
+}
+
static void ct3_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
+ CXLType3Class *cvc = CXL_TYPE3_DEV_CLASS(oc);
pc->realize = ct3_realize;
pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
@@ -201,11 +192,14 @@ static void ct3_class_init(ObjectClass *oc, void *data)
dc->desc = "CXL PMEM Device (Type 3)";
dc->reset = ct3d_reset;
device_class_set_props(dc, ct3_props);
+
+ cvc->get_lsa_size = get_lsa_size;
}
static const TypeInfo ct3d_info = {
.name = TYPE_CXL_TYPE3_DEV,
.parent = TYPE_PCI_DEVICE,
+ .class_size = sizeof(struct CXLType3Class),
.class_init = ct3_class_init,
.instance_size = sizeof(CXLType3Dev),
.instance_finalize = ct3_finalize,
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 8102d2a813..ebb391153a 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -230,4 +230,33 @@ REG64(CXL_MEM_DEV_STS, 0)
FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3)
+typedef struct cxl_type3_dev {
+ /* Private */
+ PCIDevice parent_obj;
+
+ /* Properties */
+ uint64_t size;
+ HostMemoryBackend *hostmem;
+ HostMemoryBackend *lsa;
+
+ /* State */
+ CXLComponentState cxl_cstate;
+ CXLDeviceState cxl_dstate;
+} CXLType3Dev;
+
+#ifndef TYPE_CXL_TYPE3_DEV
+#define TYPE_CXL_TYPE3_DEV "cxl-type3"
+#endif
+
+#define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV)
+OBJECT_DECLARE_TYPE(CXLType3Device, CXLType3Class, CXL_TYPE3_DEV)
+
+struct CXLType3Class {
+ /* Private */
+ PCIDeviceClass parent_class;
+
+ /* public */
+ uint64_t (*get_lsa_size)(CXLType3Dev *ct3d);
+};
+
#endif
--
2.32.0
- [PATCH v6 11/43] hw/pxb: Use a type for realizing expanders, (continued)
- [PATCH v6 11/43] hw/pxb: Use a type for realizing expanders, Jonathan Cameron, 2022/02/11
- [PATCH v6 12/43] hw/pci/cxl: Create a CXL bus type, Jonathan Cameron, 2022/02/11
- [PATCH v6 13/43] cxl: Machine level control on whether CXL support is enabled, Jonathan Cameron, 2022/02/11
- [PATCH v6 14/43] hw/pxb: Allow creation of a CXL PXB (host bridge), Jonathan Cameron, 2022/02/11
- [PATCH v6 15/43] qtest/cxl: Introduce initial test for pxb-cxl only., Jonathan Cameron, 2022/02/11
- [PATCH v6 16/43] hw/cxl/rp: Add a root port, Jonathan Cameron, 2022/02/11
- [PATCH v6 17/43] hw/cxl/device: Add a memory device (8.2.8.5), Jonathan Cameron, 2022/02/11
- [PATCH v6 18/43] qtests/cxl: Add initial root port and CXL type3 tests, Jonathan Cameron, 2022/02/11
- [PATCH v6 19/43] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12), Jonathan Cameron, 2022/02/11
- [PATCH v6 20/43] hw/cxl/device: Add some trivial commands, Jonathan Cameron, 2022/02/11
- [PATCH v6 21/43] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing,
Jonathan Cameron <=
- [PATCH v6 22/43] hw/cxl/device: Implement get/set Label Storage Area (LSA), Jonathan Cameron, 2022/02/11
- [PATCH v6 23/43] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142), Jonathan Cameron, 2022/02/11
- [PATCH v6 24/43] acpi/cxl: Add _OSC implementation (9.14.2), Jonathan Cameron, 2022/02/11
- [PATCH v6 25/43] acpi/cxl: Create the CEDT (9.14.1), Jonathan Cameron, 2022/02/11
- [PATCH v6 26/43] hw/cxl/component: Add utils for interleave parameter encoding/decoding, Jonathan Cameron, 2022/02/11
- [PATCH v6 27/43] hw/cxl/host: Add support for CXL Fixed Memory Windows., Jonathan Cameron, 2022/02/11
- [PATCH v6 28/43] acpi/cxl: Introduce CFMWS structures in CEDT, Jonathan Cameron, 2022/02/11
- [PATCH v6 29/43] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl, Jonathan Cameron, 2022/02/11
- [PATCH v6 30/43] pci/pcie_port: Add pci_find_port_by_pn(), Jonathan Cameron, 2022/02/11
- [PATCH v6 31/43] CXL/cxl_component: Add cxl_get_hb_cstate(), Jonathan Cameron, 2022/02/11