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[PATCH v6 30/43] pci/pcie_port: Add pci_find_port_by_pn()
From: |
Jonathan Cameron |
Subject: |
[PATCH v6 30/43] pci/pcie_port: Add pci_find_port_by_pn() |
Date: |
Fri, 11 Feb 2022 12:07:34 +0000 |
From: Jonathan Cameron <jonathan.cameron@huawei.com>
Simple function to search a PCIBus to find a port by
it's port number.
CXL interleave decoding uses the port number as a target
so it is necessary to locate the port when doing interleave
decoding.
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
hw/pci/pcie_port.c | 25 +++++++++++++++++++++++++
include/hw/pci/pcie_port.h | 2 ++
2 files changed, 27 insertions(+)
diff --git a/hw/pci/pcie_port.c b/hw/pci/pcie_port.c
index e95c1e5519..687e4e763a 100644
--- a/hw/pci/pcie_port.c
+++ b/hw/pci/pcie_port.c
@@ -136,6 +136,31 @@ static void pcie_port_class_init(ObjectClass *oc, void
*data)
device_class_set_props(dc, pcie_port_props);
}
+PCIDevice *pcie_find_port_by_pn(PCIBus *bus, uint8_t pn)
+{
+ int devfn;
+
+ for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
+ PCIDevice *d = bus->devices[devfn];
+ PCIEPort *port;
+
+ if (!d || !pci_is_express(d) || !d->exp.exp_cap) {
+ continue;
+ }
+
+ if (!object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) {
+ continue;
+ }
+
+ port = PCIE_PORT(d);
+ if (port->port == pn) {
+ return d;
+ }
+ }
+
+ return NULL;
+}
+
static const TypeInfo pcie_port_type_info = {
.name = TYPE_PCIE_PORT,
.parent = TYPE_PCI_BRIDGE,
diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h
index e25b289ce8..7b8193061a 100644
--- a/include/hw/pci/pcie_port.h
+++ b/include/hw/pci/pcie_port.h
@@ -39,6 +39,8 @@ struct PCIEPort {
void pcie_port_init_reg(PCIDevice *d);
+PCIDevice *pcie_find_port_by_pn(PCIBus *bus, uint8_t pn);
+
#define TYPE_PCIE_SLOT "pcie-slot"
OBJECT_DECLARE_SIMPLE_TYPE(PCIESlot, PCIE_SLOT)
--
2.32.0
- [PATCH v6 20/43] hw/cxl/device: Add some trivial commands, (continued)
- [PATCH v6 20/43] hw/cxl/device: Add some trivial commands, Jonathan Cameron, 2022/02/11
- [PATCH v6 21/43] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing, Jonathan Cameron, 2022/02/11
- [PATCH v6 22/43] hw/cxl/device: Implement get/set Label Storage Area (LSA), Jonathan Cameron, 2022/02/11
- [PATCH v6 23/43] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142), Jonathan Cameron, 2022/02/11
- [PATCH v6 24/43] acpi/cxl: Add _OSC implementation (9.14.2), Jonathan Cameron, 2022/02/11
- [PATCH v6 25/43] acpi/cxl: Create the CEDT (9.14.1), Jonathan Cameron, 2022/02/11
- [PATCH v6 26/43] hw/cxl/component: Add utils for interleave parameter encoding/decoding, Jonathan Cameron, 2022/02/11
- [PATCH v6 27/43] hw/cxl/host: Add support for CXL Fixed Memory Windows., Jonathan Cameron, 2022/02/11
- [PATCH v6 28/43] acpi/cxl: Introduce CFMWS structures in CEDT, Jonathan Cameron, 2022/02/11
- [PATCH v6 29/43] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl, Jonathan Cameron, 2022/02/11
- [PATCH v6 30/43] pci/pcie_port: Add pci_find_port_by_pn(),
Jonathan Cameron <=
- [PATCH v6 31/43] CXL/cxl_component: Add cxl_get_hb_cstate(), Jonathan Cameron, 2022/02/11
- [PATCH v6 32/43] mem/cxl_type3: Add read and write functions for associated hostmem., Jonathan Cameron, 2022/02/11
- [PATCH v6 33/43] cxl/cxl-host: Add memops for CFMWS region., Jonathan Cameron, 2022/02/11
- [PATCH v6 34/43] RFC: softmmu/memory: Add ops to memory_region_ram_init_from_file, Jonathan Cameron, 2022/02/11
- [PATCH v6 35/43] hw/cxl/component Add a dumb HDM decoder handler, Jonathan Cameron, 2022/02/11
- [PATCH v6 36/43] i386/pc: Enable CXL fixed memory windows, Jonathan Cameron, 2022/02/11
- [PATCH v6 37/43] tests/acpi: q35: Allow addition of a CXL test., Jonathan Cameron, 2022/02/11
- [PATCH v6 38/43] qtests/bios-tables-test: Add a test for CXL emulation., Jonathan Cameron, 2022/02/11
- [PATCH v6 39/43] tests/acpi: Add tables for CXL emulation., Jonathan Cameron, 2022/02/11
- [PATCH v6 40/43] qtest/cxl: Add more complex test cases with CFMWs, Jonathan Cameron, 2022/02/11