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[PATCH v6 33/43] cxl/cxl-host: Add memops for CFMWS region.
From: |
Jonathan Cameron |
Subject: |
[PATCH v6 33/43] cxl/cxl-host: Add memops for CFMWS region. |
Date: |
Fri, 11 Feb 2022 12:07:37 +0000 |
From: Jonathan Cameron <jonathan.cameron@huawei.com>
These memops perform interleave decoding, walking down the
CXL topology from CFMWS described host interleave
decoder via CXL host bridge HDM decoders, through the CXL
root ports and finally call CXL type 3 specific read and write
functions.
Note that, whilst functional the current implementation does
not support:
* switches
* multiple HDM decoders at a given level.
* unaligned accesses across the interleave boundaries
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
hw/cxl/cxl-host.c | 124 +++++++++++++++++++++++++++++++++++++++++++
include/hw/cxl/cxl.h | 2 +
2 files changed, 126 insertions(+)
diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
index 9f303e6d8e..ec6871ff36 100644
--- a/hw/cxl/cxl-host.c
+++ b/hw/cxl/cxl-host.c
@@ -136,3 +136,127 @@ void cxl_fixed_memory_window_link_targets(Error **errp)
}
}
}
+
+/* TODO: support, multiple hdm decoders */
+static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
+ uint8_t *target)
+{
+ uint32_t ctrl;
+ uint32_t ig_enc;
+ uint32_t iw_enc;
+ uint32_t target_reg;
+ uint32_t target_idx;
+
+ ctrl = cache_mem[R_CXL_HDM_DECODER0_CTRL];
+ if (!FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED)) {
+ return false;
+ }
+
+ ig_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IG);
+ iw_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW);
+ target_idx = (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc);
+
+ if (target_idx > 4) {
+ target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
+ target_reg >>= target_idx * 8;
+ } else {
+ target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
+ target_reg >>= (target_idx - 4) * 8;
+ }
+ *target = target_reg & 0xff;
+
+ return true;
+}
+
+static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr)
+{
+ CXLComponentState *hb_cstate;
+ PCIHostState *hb;
+ int rb_index;
+ uint32_t *cache_mem;
+ uint8_t target;
+ bool target_found;
+ PCIDevice *rp, *d;
+
+ /* Address is relative to memory region. Convert to HPA */
+ addr += fw->base;
+
+ rb_index = (addr / cxl_decode_ig(fw->enc_int_gran)) % fw->num_targets;
+ hb = PCI_HOST_BRIDGE(fw->target_hbs[rb_index]->cxl.cxl_host_bridge);
+ if (!hb || !hb->bus || !pci_bus_is_cxl(hb->bus)) {
+ return NULL;
+ }
+
+ hb_cstate = cxl_get_hb_cstate(hb);
+ if (!hb_cstate) {
+ return NULL;
+ }
+
+ cache_mem = hb_cstate->crb.cache_mem_registers;
+
+ target_found = cxl_hdm_find_target(cache_mem, addr, &target);
+ if (!target_found) {
+ return NULL;
+ }
+
+ rp = pcie_find_port_by_pn(hb->bus, target);
+ if (!rp) {
+ return NULL;
+ }
+
+ d = pci_bridge_get_sec_bus(PCI_BRIDGE(rp))->devices[0];
+
+ if (!d || !object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3_DEV)) {
+ return NULL;
+ }
+
+ return d;
+}
+
+static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+ CXLFixedWindow *fw = opaque;
+ PCIDevice *d;
+
+ d = cxl_cfmws_find_device(fw, addr);
+ if (d == NULL) {
+ *data = 0;
+ /* Reads to invalid address return poison */
+ return MEMTX_ERROR;
+ }
+
+ return cxl_type3_read(d, addr + fw->base, data, size, attrs);
+}
+
+static MemTxResult cxl_write_cfmws(void *opaque, hwaddr addr,
+ uint64_t data, unsigned size,
+ MemTxAttrs attrs)
+{
+ CXLFixedWindow *fw = opaque;
+ PCIDevice *d;
+
+ d = cxl_cfmws_find_device(fw, addr);
+ if (d == NULL) {
+ /* Writes to invalid address are silent */
+ return MEMTX_OK;
+ }
+
+ return cxl_type3_write(d, addr + fw->base, data, size, attrs);
+}
+
+const MemoryRegionOps cfmws_ops = {
+ .read_with_attrs = cxl_read_cfmws,
+ .write_with_attrs = cxl_write_cfmws,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ .unaligned = true,
+ },
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ .unaligned = true,
+ },
+};
diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h
index 1b72c0b7b7..260d602ec9 100644
--- a/include/hw/cxl/cxl.h
+++ b/include/hw/cxl/cxl.h
@@ -46,4 +46,6 @@ extern QemuOptsList qemu_cxl_fixed_window_opts;
void parse_cxl_fixed_memory_window_opts(MachineState *ms);
void cxl_fixed_memory_window_link_targets(Error **errp);
+extern const MemoryRegionOps cfmws_ops;
+
#endif
--
2.32.0
- [PATCH v6 23/43] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142), (continued)
- [PATCH v6 23/43] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142), Jonathan Cameron, 2022/02/11
- [PATCH v6 24/43] acpi/cxl: Add _OSC implementation (9.14.2), Jonathan Cameron, 2022/02/11
- [PATCH v6 25/43] acpi/cxl: Create the CEDT (9.14.1), Jonathan Cameron, 2022/02/11
- [PATCH v6 26/43] hw/cxl/component: Add utils for interleave parameter encoding/decoding, Jonathan Cameron, 2022/02/11
- [PATCH v6 27/43] hw/cxl/host: Add support for CXL Fixed Memory Windows., Jonathan Cameron, 2022/02/11
- [PATCH v6 28/43] acpi/cxl: Introduce CFMWS structures in CEDT, Jonathan Cameron, 2022/02/11
- [PATCH v6 29/43] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl, Jonathan Cameron, 2022/02/11
- [PATCH v6 30/43] pci/pcie_port: Add pci_find_port_by_pn(), Jonathan Cameron, 2022/02/11
- [PATCH v6 31/43] CXL/cxl_component: Add cxl_get_hb_cstate(), Jonathan Cameron, 2022/02/11
- [PATCH v6 32/43] mem/cxl_type3: Add read and write functions for associated hostmem., Jonathan Cameron, 2022/02/11
- [PATCH v6 33/43] cxl/cxl-host: Add memops for CFMWS region.,
Jonathan Cameron <=
- [PATCH v6 34/43] RFC: softmmu/memory: Add ops to memory_region_ram_init_from_file, Jonathan Cameron, 2022/02/11
- [PATCH v6 35/43] hw/cxl/component Add a dumb HDM decoder handler, Jonathan Cameron, 2022/02/11
- [PATCH v6 36/43] i386/pc: Enable CXL fixed memory windows, Jonathan Cameron, 2022/02/11
- [PATCH v6 37/43] tests/acpi: q35: Allow addition of a CXL test., Jonathan Cameron, 2022/02/11
- [PATCH v6 38/43] qtests/bios-tables-test: Add a test for CXL emulation., Jonathan Cameron, 2022/02/11
- [PATCH v6 39/43] tests/acpi: Add tables for CXL emulation., Jonathan Cameron, 2022/02/11
- [PATCH v6 40/43] qtest/cxl: Add more complex test cases with CFMWs, Jonathan Cameron, 2022/02/11
- [PATCH v6 41/43] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl, Jonathan Cameron, 2022/02/11
- [PATCH v6 42/43] qtest/cxl: Add aarch64 virt test for CXL, Jonathan Cameron, 2022/02/11
- [PATCH v6 43/43] docs/cxl: Add initial Compute eXpress Link (CXL) documentation., Jonathan Cameron, 2022/02/11