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Re: [PATCH 04/27] target/ppc: cpu_init: Move Timebase registration into
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From: |
David Gibson |
|
Subject: |
Re: [PATCH 04/27] target/ppc: cpu_init: Move Timebase registration into the common function |
|
Date: |
Wed, 16 Feb 2022 13:11:07 +1100 |
On Tue, Feb 15, 2022 at 06:41:25PM -0300, Fabiano Rosas wrote:
> Now that the 601 was removed, all of our CPUs have a timebase, so that
> can be moved into the common function.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target/ppc/cpu_init.c | 98 ++++++++-----------------------------------
> 1 file changed, 18 insertions(+), 80 deletions(-)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 5dc097f2fc..b7e460e12d 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -221,6 +221,24 @@ static void register_generic_sprs(PowerPCCPU *cpu)
> pcc->svr);
> }
> }
> +
> + /* Time base */
> + spr_register(env, SPR_VTBL, "TBL",
> + &spr_read_tbl, SPR_NOACCESS,
> + &spr_read_tbl, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_TBL, "TBL",
> + &spr_read_tbl, SPR_NOACCESS,
> + &spr_read_tbl, &spr_write_tbl,
> + 0x00000000);
> + spr_register(env, SPR_VTBU, "TBU",
> + &spr_read_tbu, SPR_NOACCESS,
> + &spr_read_tbu, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_TBU, "TBU",
> + &spr_read_tbu, SPR_NOACCESS,
> + &spr_read_tbu, &spr_write_tbu,
> + 0x00000000);
> }
>
> /* SPR common to all non-embedded PowerPC, including 601 */
> @@ -409,27 +427,6 @@ static void register_high_BATs(CPUPPCState *env)
> #endif
> }
>
> -/* Generic PowerPC time base */
> -static void register_tbl(CPUPPCState *env)
> -{
> - spr_register(env, SPR_VTBL, "TBL",
> - &spr_read_tbl, SPR_NOACCESS,
> - &spr_read_tbl, SPR_NOACCESS,
> - 0x00000000);
> - spr_register(env, SPR_TBL, "TBL",
> - &spr_read_tbl, SPR_NOACCESS,
> - &spr_read_tbl, &spr_write_tbl,
> - 0x00000000);
> - spr_register(env, SPR_VTBU, "TBU",
> - &spr_read_tbu, SPR_NOACCESS,
> - &spr_read_tbu, SPR_NOACCESS,
> - 0x00000000);
> - spr_register(env, SPR_TBU, "TBU",
> - &spr_read_tbu, SPR_NOACCESS,
> - &spr_read_tbu, &spr_write_tbu,
> - 0x00000000);
> -}
> -
> /* Softare table search registers */
> static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int
> nb_ways)
> {
> @@ -2323,8 +2320,6 @@ static int check_pow_hid0_74xx(CPUPPCState *env)
>
> static void init_proc_405(CPUPPCState *env)
> {
> - /* Time base */
> - register_tbl(env);
> register_40x_sprs(env);
> register_405_sprs(env);
> /* Bus access control */
> @@ -2390,8 +2385,6 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
>
> static void init_proc_440EP(CPUPPCState *env)
> {
> - /* Time base */
> - register_tbl(env);
> register_BookE_sprs(env, 0x000000000000FFFFULL);
> register_440_sprs(env);
> register_usprgh_sprs(env);
> @@ -2532,8 +2525,6 @@ POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
>
> static void init_proc_440GP(CPUPPCState *env)
> {
> - /* Time base */
> - register_tbl(env);
> register_BookE_sprs(env, 0x000000000000FFFFULL);
> register_440_sprs(env);
> register_usprgh_sprs(env);
> @@ -2615,8 +2606,6 @@ POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
>
> static void init_proc_440x5(CPUPPCState *env)
> {
> - /* Time base */
> - register_tbl(env);
> register_BookE_sprs(env, 0x000000000000FFFFULL);
> register_440_sprs(env);
> register_usprgh_sprs(env);
> @@ -2754,8 +2743,6 @@ POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
>
> static void init_proc_MPC5xx(CPUPPCState *env)
> {
> - /* Time base */
> - register_tbl(env);
> register_5xx_8xx_sprs(env);
> register_5xx_sprs(env);
> init_excp_MPC5xx(env);
> @@ -2798,8 +2785,6 @@ POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
>
> static void init_proc_MPC8xx(CPUPPCState *env)
> {
> - /* Time base */
> - register_tbl(env);
> register_5xx_8xx_sprs(env);
> register_8xx_sprs(env);
> init_excp_MPC8xx(env);
> @@ -2847,8 +2832,6 @@ static void init_proc_G2(CPUPPCState *env)
> register_sdr1_sprs(env);
> register_G2_755_sprs(env);
> register_G2_sprs(env);
> - /* Time base */
> - register_tbl(env);
> /* External access control */
> spr_register(env, SPR_EAR, "EAR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -2960,8 +2943,6 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
>
> static void init_proc_e200(CPUPPCState *env)
> {
> - /* Time base */
> - register_tbl(env);
> register_BookE_sprs(env, 0x000000070000FFFFULL);
>
> spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
> @@ -3118,8 +3099,6 @@ static void init_proc_e300(CPUPPCState *env)
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> register_603_sprs(env);
> - /* Time base */
> - register_tbl(env);
> /* hardware implementation registers */
> spr_register(env, SPR_HID0, "HID0",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -3233,8 +3212,6 @@ static void init_proc_e500(CPUPPCState *env, int
> version)
> int i;
> #endif
>
> - /* Time base */
> - register_tbl(env);
> /*
> * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
> * complain when accessing them.
> @@ -3678,8 +3655,6 @@ static void init_proc_603(CPUPPCState *env)
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> register_603_sprs(env);
> - /* Time base */
> - register_tbl(env);
> /* hardware implementation registers */
> spr_register(env, SPR_HID0, "HID0",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -3783,8 +3758,6 @@ static void init_proc_604(CPUPPCState *env)
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> register_604_sprs(env);
> - /* Time base */
> - register_tbl(env);
> /* Hardware implementation registers */
> spr_register(env, SPR_HID0, "HID0",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -3858,8 +3831,6 @@ static void init_proc_604E(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> - /* Time base */
> - register_tbl(env);
> /* Hardware implementation registers */
> spr_register(env, SPR_HID0, "HID0",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -3923,8 +3894,6 @@ static void init_proc_740(CPUPPCState *env)
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> register_7xx_sprs(env);
> - /* Time base */
> - register_tbl(env);
> /* Thermal management */
> register_thrm_sprs(env);
> /* Hardware implementation registers */
> @@ -3995,8 +3964,6 @@ static void init_proc_750(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, spr_access_nop,
> 0x00000000);
> - /* Time base */
> - register_tbl(env);
> /* Thermal management */
> register_thrm_sprs(env);
> /* Hardware implementation registers */
> @@ -4071,8 +4038,6 @@ static void init_proc_750cl(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, spr_access_nop,
> 0x00000000);
> - /* Time base */
> - register_tbl(env);
> /* Thermal management */
> /* Those registers are fake on 750CL */
> spr_register(env, SPR_THRM1, "THRM1",
> @@ -4268,8 +4233,6 @@ static void init_proc_750cx(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, spr_access_nop,
> 0x00000000);
> - /* Time base */
> - register_tbl(env);
> /* Thermal management */
> register_thrm_sprs(env);
>
> @@ -4347,8 +4310,6 @@ static void init_proc_750fx(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, spr_access_nop,
> 0x00000000);
> - /* Time base */
> - register_tbl(env);
> /* Thermal management */
> register_thrm_sprs(env);
>
> @@ -4431,8 +4392,6 @@ static void init_proc_750gx(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, spr_access_nop,
> 0x00000000);
> - /* Time base */
> - register_tbl(env);
> /* Thermal management */
> register_thrm_sprs(env);
>
> @@ -4511,8 +4470,6 @@ static void init_proc_745(CPUPPCState *env)
> register_sdr1_sprs(env);
> register_7xx_sprs(env);
> register_G2_755_sprs(env);
> - /* Time base */
> - register_tbl(env);
> /* Thermal management */
> register_thrm_sprs(env);
> /* Hardware implementation registers */
> @@ -4586,8 +4543,6 @@ static void init_proc_755(CPUPPCState *env)
> register_sdr1_sprs(env);
> register_7xx_sprs(env);
> register_G2_755_sprs(env);
> - /* Time base */
> - register_tbl(env);
> /* L2 cache control */
> spr_register(env, SPR_L2CR, "L2CR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -4670,8 +4625,6 @@ static void init_proc_7400(CPUPPCState *env)
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> register_7xx_sprs(env);
> - /* Time base */
> - register_tbl(env);
> /* 74xx specific SPR */
> register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> @@ -4746,8 +4699,6 @@ static void init_proc_7410(CPUPPCState *env)
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> register_7xx_sprs(env);
> - /* Time base */
> - register_tbl(env);
> /* 74xx specific SPR */
> register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> @@ -4829,8 +4780,6 @@ static void init_proc_7440(CPUPPCState *env)
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> register_7xx_sprs(env);
> - /* Time base */
> - register_tbl(env);
> /* 74xx specific SPR */
> register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> @@ -4933,8 +4882,6 @@ static void init_proc_7450(CPUPPCState *env)
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> register_7xx_sprs(env);
> - /* Time base */
> - register_tbl(env);
> /* 74xx specific SPR */
> register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> @@ -5059,8 +5006,6 @@ static void init_proc_7445(CPUPPCState *env)
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> register_7xx_sprs(env);
> - /* Time base */
> - register_tbl(env);
> /* 74xx specific SPR */
> register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> @@ -5192,8 +5137,6 @@ static void init_proc_7455(CPUPPCState *env)
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> register_7xx_sprs(env);
> - /* Time base */
> - register_tbl(env);
> /* 74xx specific SPR */
> register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> @@ -5327,8 +5270,6 @@ static void init_proc_7457(CPUPPCState *env)
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> register_7xx_sprs(env);
> - /* Time base */
> - register_tbl(env);
> /* 74xx specific SPR */
> register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> @@ -5482,8 +5423,6 @@ static void init_proc_e600(CPUPPCState *env)
> register_ne_601_sprs(env);
> register_sdr1_sprs(env);
> register_7xx_sprs(env);
> - /* Time base */
> - register_tbl(env);
> /* 74xx specific SPR */
> register_74xx_sprs(env);
> vscr_init(env, 0x00010000);
> @@ -6307,7 +6246,6 @@ static void init_tcg_pmu_power8(CPUPPCState *env)
> static void init_proc_book3s_common(CPUPPCState *env)
> {
> register_ne_601_sprs(env);
> - register_tbl(env);
> register_usprg3_sprs(env);
> register_book3s_altivec_sprs(env);
> register_book3s_pmu_sup_sprs(env);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [PATCH 00/27] target/ppc: SPR registration cleanups, Fabiano Rosas, 2022/02/15
- [PATCH 03/27] target/ppc: cpu_init: Group registration of generic SPRs, Fabiano Rosas, 2022/02/15
- [PATCH 02/27] target/ppc: cpu_init: Remove G2LE init code, Fabiano Rosas, 2022/02/15
- [PATCH 01/27] target/ppc: cpu_init: Remove not implemented comments, Fabiano Rosas, 2022/02/15
- [PATCH 04/27] target/ppc: cpu_init: Move Timebase registration into the common function, Fabiano Rosas, 2022/02/15
- Re: [PATCH 04/27] target/ppc: cpu_init: Move Timebase registration into the common function,
David Gibson <=
- [PATCH 05/27] target/ppc: cpu_init: Avoid nested SPR register functions, Fabiano Rosas, 2022/02/15
- [PATCH 06/27] target/ppc: cpu_init: Move 405 SPRs into register_405_sprs, Fabiano Rosas, 2022/02/15
- [PATCH 07/27] target/ppc: cpu_init: Move G2 SPRs into register_G2_sprs, Fabiano Rosas, 2022/02/15
- [PATCH 10/27] target/ppc: cpu_init: Deduplicate 440 SPR registration, Fabiano Rosas, 2022/02/15
- [PATCH 09/27] target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx, Fabiano Rosas, 2022/02/15