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[PATCH 5/7] target/ppc: split XXGENPCV macros for readability
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From: |
matheus . ferst |
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Subject: |
[PATCH 5/7] target/ppc: split XXGENPCV macros for readability |
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Date: |
Fri, 4 Mar 2022 14:51:54 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Fixes: b090f4f1e3c9 ("target/ppc: Implement xxgenpcv[bhwd]m instruction")
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/int_helper.c | 28 +++++++++---
target/ppc/translate/vsx-impl.c.inc | 71 +++++++++++++++--------------
2 files changed, 57 insertions(+), 42 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index b2b17bb1ca..492f34c499 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1072,7 +1072,7 @@ void helper_VPERMR(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t
*b, ppc_avr_t *c)
*r = result;
}
-#define XXGENPCV(NAME, SZ) \
+#define XXGENPCV_BE_EXP(NAME, SZ) \
void glue(helper_, glue(NAME, _be_exp))(ppc_vsr_t *t, ppc_vsr_t *b) \
{ \
ppc_vsr_t tmp; \
@@ -1093,8 +1093,9 @@ void glue(helper_, glue(NAME, _be_exp))(ppc_vsr_t *t,
ppc_vsr_t *b) \
} \
\
*t = tmp; \
-} \
- \
+}
+
+#define XXGENPCV_BE_COMP(NAME, SZ) \
void glue(helper_, glue(NAME, _be_comp))(ppc_vsr_t *t, ppc_vsr_t *b)\
{ \
ppc_vsr_t tmp = { .u64 = { 0, 0 } }; \
@@ -1111,8 +1112,9 @@ void glue(helper_, glue(NAME, _be_comp))(ppc_vsr_t *t,
ppc_vsr_t *b)\
} \
\
*t = tmp; \
-} \
- \
+}
+
+#define XXGENPCV_LE_EXP(NAME, SZ) \
void glue(helper_, glue(NAME, _le_exp))(ppc_vsr_t *t, ppc_vsr_t *b) \
{ \
ppc_vsr_t tmp; \
@@ -1135,8 +1137,9 @@ void glue(helper_, glue(NAME, _le_exp))(ppc_vsr_t *t,
ppc_vsr_t *b) \
} \
\
*t = tmp; \
-} \
- \
+}
+
+#define XXGENPCV_LE_COMP(NAME, SZ) \
void glue(helper_, glue(NAME, _le_comp))(ppc_vsr_t *t, ppc_vsr_t *b)\
{ \
ppc_vsr_t tmp = { .u64 = { 0, 0 } }; \
@@ -1157,10 +1160,21 @@ void glue(helper_, glue(NAME, _le_comp))(ppc_vsr_t *t,
ppc_vsr_t *b)\
*t = tmp; \
}
+#define XXGENPCV(NAME, SZ) \
+ XXGENPCV_BE_EXP(NAME, SZ) \
+ XXGENPCV_BE_COMP(NAME, SZ) \
+ XXGENPCV_LE_EXP(NAME, SZ) \
+ XXGENPCV_LE_COMP(NAME, SZ) \
+
XXGENPCV(XXGENPCVBM, 1)
XXGENPCV(XXGENPCVHM, 2)
XXGENPCV(XXGENPCVWM, 4)
XXGENPCV(XXGENPCVDM, 8)
+
+#undef XXGENPCV_BE_EXP
+#undef XXGENPCV_BE_COMP
+#undef XXGENPCV_LE_EXP
+#undef XXGENPCV_LE_COMP
#undef XXGENPCV
#if defined(HOST_WORDS_BIGENDIAN)
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index 2ffeab5287..48a97b2d7e 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1204,43 +1204,44 @@ static bool trans_XXPERMX(DisasContext *ctx,
arg_8RR_XX4_uim3 *a)
return true;
}
-#define XXGENPCV(NAME) \
-static bool trans_##NAME(DisasContext *ctx, arg_X_imm5 *a) \
-{ \
- TCGv_ptr xt, vrb; \
- \
- REQUIRE_INSNS_FLAGS2(ctx, ISA310); \
- REQUIRE_VSX(ctx); \
- \
- if (a->imm & ~0x3) { \
- gen_invalid(ctx); \
- return true; \
- } \
- \
- xt = gen_vsr_ptr(a->xt); \
- vrb = gen_avr_ptr(a->vrb); \
- \
- switch (a->imm) { \
- case 0b00000: /* Big-Endian expansion */ \
- glue(gen_helper_, glue(NAME, _be_exp))(xt, vrb); \
- break; \
- case 0b00001: /* Big-Endian compression */ \
- glue(gen_helper_, glue(NAME, _be_comp))(xt, vrb); \
- break; \
- case 0b00010: /* Little-Endian expansion */ \
- glue(gen_helper_, glue(NAME, _le_exp))(xt, vrb); \
- break; \
- case 0b00011: /* Little-Endian compression */ \
- glue(gen_helper_, glue(NAME, _le_comp))(xt, vrb); \
- break; \
- } \
- \
- tcg_temp_free_ptr(xt); \
- tcg_temp_free_ptr(vrb); \
- \
- return true; \
+typedef void (*xxgenpcv_genfn)(TCGv_ptr, TCGv_ptr);
+
+static bool do_xxgenpcv(DisasContext *ctx, arg_X_imm5 *a,
+ const xxgenpcv_genfn fn[4])
+{
+ TCGv_ptr xt, vrb;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ if (a->imm & ~0x3) {
+ gen_invalid(ctx);
+ return true;
+ }
+
+ xt = gen_vsr_ptr(a->xt);
+ vrb = gen_avr_ptr(a->vrb);
+
+ fn[a->imm](xt, vrb);
+
+ tcg_temp_free_ptr(xt);
+ tcg_temp_free_ptr(vrb);
+
+ return true;
}
+#define XXGENPCV(NAME) \
+ static bool trans_##NAME(DisasContext *ctx, arg_X_imm5 *a) \
+ { \
+ static const xxgenpcv_genfn fn[4] = { \
+ gen_helper_##NAME##_be_exp, \
+ gen_helper_##NAME##_be_comp, \
+ gen_helper_##NAME##_le_exp, \
+ gen_helper_##NAME##_le_comp, \
+ }; \
+ return do_xxgenpcv(ctx, a, fn); \
+ }
+
XXGENPCV(XXGENPCVBM)
XXGENPCV(XXGENPCVHM)
XXGENPCV(XXGENPCVWM)
--
2.25.1
- [PATCH 1/7] target/ppc: Fix vmul[eo]* instructions marked 2.07, (continued)
- [PATCH 1/7] target/ppc: Fix vmul[eo]* instructions marked 2.07, matheus . ferst, 2022/03/04
- [PATCH 2/7] target/ppc: use ext32u and deposit in do_vx_vmulhw_i64, matheus . ferst, 2022/03/04
- [PATCH 3/7] target/ppc: use extract/extract2 to create vrlqnm mask, matheus . ferst, 2022/03/04
- [PATCH 4/7] target/ppc: use andc in vrlqmi, matheus . ferst, 2022/03/04
- [PATCH 5/7] target/ppc: split XXGENPCV macros for readability,
matheus . ferst <=
- [PATCH 6/7] target/ppc: Add missing helper_reset_fpstatus to VSX_MAX_MINC, matheus . ferst, 2022/03/04
- [PATCH 7/7] target/ppc: Add missing helper_reset_fpstatus to helper_XVCVSPBF16, matheus . ferst, 2022/03/04
- Re: [PATCH 0/7] target/ppc: Vector/VSX instruction batch fixes, Cédric Le Goater, 2022/03/05