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[PATCH v7 38/46] qtests/bios-tables-test: Add a test for CXL emulation.
From: |
Jonathan Cameron |
Subject: |
[PATCH v7 38/46] qtests/bios-tables-test: Add a test for CXL emulation. |
Date: |
Sun, 6 Mar 2022 17:41:29 +0000 |
The DSDT includes several CXL specific elements and the CEDT
table is only present if we enable CXL.
The test exercises all current functionality with several
CFMWS, CHBS structures in CEDT and ACPI0016/ACPI00017 and _OSC
entries in DSDT.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
tests/qtest/bios-tables-test.c | 44 ++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index c4a2d1e166..d43503a42d 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1537,6 +1537,49 @@ static void test_acpi_q35_viot(void)
free_test_data(&data);
}
+static void test_acpi_q35_cxl(void)
+{
+ gchar *tmp_path = g_dir_make_tmp("qemu-test-cxl.XXXXXX", NULL);
+ gchar *params;
+
+ test_data data = {
+ .machine = MACHINE_Q35,
+ .variant = ".cxl",
+ };
+ /*
+ * A complex CXL setup.
+ */
+ params = g_strdup_printf(" -machine cxl=on"
+ " -object
memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M"
+ " -object
memory-backend-file,id=cxl-mem2,mem-path=%s,size=256M"
+ " -object
memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M"
+ " -object
memory-backend-file,id=cxl-mem4,mem-path=%s,size=256M"
+ " -object
memory-backend-file,id=lsa1,mem-path=%s,size=256M"
+ " -object
memory-backend-file,id=lsa2,mem-path=%s,size=256M"
+ " -object
memory-backend-file,id=lsa3,mem-path=%s,size=256M"
+ " -object
memory-backend-file,id=lsa4,mem-path=%s,size=256M"
+ " -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1"
+ " -device pxb-cxl,bus_nr=222,bus=pcie.0,id=cxl.2"
+ " -device
cxl-rp,port=0,bus=cxl.1,id=rp1,chassis=0,slot=2"
+ " -device
cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,size=256M"
+ " -device
cxl-rp,port=1,bus=cxl.1,id=rp2,chassis=0,slot=3"
+ " -device
cxl-type3,bus=rp2,memdev=cxl-mem2,lsa=lsa2,size=256M"
+ " -device
cxl-rp,port=0,bus=cxl.2,id=rp3,chassis=0,slot=5"
+ " -device
cxl-type3,bus=rp3,memdev=cxl-mem3,lsa=lsa3,size=256M"
+ " -device
cxl-rp,port=1,bus=cxl.2,id=rp4,chassis=0,slot=6"
+ " -device
cxl-type3,bus=rp4,memdev=cxl-mem4,lsa=lsa4,size=256M"
+ " -cxl-fixed-memory-window
targets.0=cxl.1,size=4G,interleave-granularity=8k"
+ " -cxl-fixed-memory-window
targets.0=cxl.1,targets.1=cxl.2,size=4G,interleave-granularity=8k",
+ tmp_path, tmp_path, tmp_path, tmp_path,
+ tmp_path, tmp_path, tmp_path, tmp_path);
+ test_acpi_one(params, &data);
+
+ g_free(params);
+ g_assert(g_rmdir(tmp_path) == 0);
+ g_free(tmp_path);
+ free_test_data(&data);
+}
+
static void test_acpi_virt_viot(void)
{
test_data data = {
@@ -1742,6 +1785,7 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
}
qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
+ qtest_add_func("acpi/q35/cxl", test_acpi_q35_cxl);
qtest_add_func("acpi/q35/slic", test_acpi_q35_slic);
} else if (strcmp(arch, "aarch64") == 0) {
if (has_tcg) {
--
2.32.0
- [PATCH v7 28/46] acpi/cxl: Introduce CFMWS structures in CEDT, (continued)
- [PATCH v7 28/46] acpi/cxl: Introduce CFMWS structures in CEDT, Jonathan Cameron, 2022/03/06
- [PATCH v7 29/46] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl, Jonathan Cameron, 2022/03/06
- [PATCH v7 30/46] pci/pcie_port: Add pci_find_port_by_pn(), Jonathan Cameron, 2022/03/06
- [PATCH v7 31/46] CXL/cxl_component: Add cxl_get_hb_cstate(), Jonathan Cameron, 2022/03/06
- [PATCH v7 32/46] mem/cxl_type3: Add read and write functions for associated hostmem., Jonathan Cameron, 2022/03/06
- [PATCH v7 33/46] cxl/cxl-host: Add memops for CFMWS region., Jonathan Cameron, 2022/03/06
- [PATCH v7 34/46] RFC: softmmu/memory: Add ops to memory_region_ram_init_from_file, Jonathan Cameron, 2022/03/06
- [PATCH v7 35/46] hw/cxl/component Add a dumb HDM decoder handler, Jonathan Cameron, 2022/03/06
- [PATCH v7 36/46] i386/pc: Enable CXL fixed memory windows, Jonathan Cameron, 2022/03/06
- [PATCH v7 37/46] tests/acpi: q35: Allow addition of a CXL test., Jonathan Cameron, 2022/03/06
- [PATCH v7 38/46] qtests/bios-tables-test: Add a test for CXL emulation.,
Jonathan Cameron <=
- [PATCH v7 39/46] tests/acpi: Add tables for CXL emulation., Jonathan Cameron, 2022/03/06
- [PATCH v7 40/46] qtest/cxl: Add more complex test cases with CFMWs, Jonathan Cameron, 2022/03/06
- [PATCH v7 41/46] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl, Jonathan Cameron, 2022/03/06
- [PATCH v7 42/46] qtest/cxl: Add aarch64 virt test for CXL, Jonathan Cameron, 2022/03/06
- [PATCH v7 43/46] docs/cxl: Add initial Compute eXpress Link (CXL) documentation., Jonathan Cameron, 2022/03/06
- [PATCH v7 44/46] pci-bridge/cxl_upstream: Add a CXL switch upstream port, Jonathan Cameron, 2022/03/06
- [PATCH v7 45/46] pci-bridge/cxl_downstream: Add a CXL switch downstream port, Jonathan Cameron, 2022/03/06
- [PATCH v7 46/46] cxl/cxl-host: Support interleave decoding with one level of switches., Jonathan Cameron, 2022/03/06
- Re: [PATCH v7 00/46] CXl 2.0 emulation Support, Michael S. Tsirkin, 2022/03/06