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[PATCH v4 15/33] target/nios2: Use hw/registerfields.h for CR_TLBMISC fi
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From: |
Richard Henderson |
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Subject: |
[PATCH v4 15/33] target/nios2: Use hw/registerfields.h for CR_TLBMISC fields |
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Date: |
Mon, 7 Mar 2022 21:19:47 -1000 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 28 ++++++++++++++++++----------
target/nios2/helper.c | 7 ++-----
target/nios2/mmu.c | 33 +++++++++++++++------------------
target/nios2/translate.c | 2 +-
4 files changed, 36 insertions(+), 34 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 024ef3ccc0..3857848f7c 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -131,16 +131,24 @@ FIELD(CR_TLBACC, IG, 25, 7)
#define CR_TLBACC_G (1u << R_CR_TLBACC_G_SHIFT)
#define CR_TLBMISC 10
-#define CR_TLBMISC_WAY_SHIFT 20
-#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT)
-#define CR_TLBMISC_RD (1 << 19)
-#define CR_TLBMISC_WR (1 << 18)
-#define CR_TLBMISC_PID_SHIFT 4
-#define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT)
-#define CR_TLBMISC_DBL (1 << 3)
-#define CR_TLBMISC_BAD (1 << 2)
-#define CR_TLBMISC_PERM (1 << 1)
-#define CR_TLBMISC_D (1 << 0)
+
+FIELD(CR_TLBMISC, D, 0, 1)
+FIELD(CR_TLBMISC, PERM, 1, 1)
+FIELD(CR_TLBMISC, BAD, 2, 1)
+FIELD(CR_TLBMISC, DBL, 3, 1)
+FIELD(CR_TLBMISC, PID, 4, 14)
+FIELD(CR_TLBMISC, WR, 18, 1)
+FIELD(CR_TLBMISC, RD, 19, 1)
+FIELD(CR_TLBMISC, WAY, 20, 4)
+FIELD(CR_TLBMISC, EE, 24, 1)
+
+#define CR_TLBMISC_RD (1u << R_CR_TLBMISC_RD_SHIFT)
+#define CR_TLBMISC_WR (1u << R_CR_TLBMISC_WR_SHIFT)
+#define CR_TLBMISC_DBL (1u << R_CR_TLBMISC_DBL_SHIFT)
+#define CR_TLBMISC_BAD (1u << R_CR_TLBMISC_BAD_SHIFT)
+#define CR_TLBMISC_PERM (1u << R_CR_TLBMISC_PERM_SHIFT)
+#define CR_TLBMISC_D (1u << R_CR_TLBMISC_D_SHIFT)
+
#define CR_ENCINJ 11
#define CR_BADADDR 12
#define CR_CONFIG 13
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 37fb53dadb..93338e86f0 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -276,11 +276,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
return false;
}
- if (access_type == MMU_INST_FETCH) {
- env->tlbmisc &= ~CR_TLBMISC_D;
- } else {
- env->tlbmisc |= CR_TLBMISC_D;
- }
+ env->tlbmisc = FIELD_DP32(env->tlbmisc, CR_TLBMISC, D,
+ access_type == MMU_INST_FETCH);
env->pteaddr = FIELD_DP32(env->pteaddr, CR_PTEADDR, VPN,
address >> TARGET_PAGE_BITS);
env->mmu.pteaddr_wr = env->pteaddr;
diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c
index d6221936f7..c8b74b5479 100644
--- a/target/nios2/mmu.c
+++ b/target/nios2/mmu.c
@@ -33,7 +33,7 @@ unsigned int mmu_translate(CPUNios2State *env,
target_ulong vaddr, int rw, int mmu_idx)
{
Nios2CPU *cpu = env_archcpu(env);
- int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
+ int pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID);
int vpn = vaddr >> 12;
int way, n_ways = cpu->tlb_num_ways;
@@ -96,9 +96,9 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
if (env->tlbmisc & CR_TLBMISC_WR) {
- int way = (env->tlbmisc >> CR_TLBMISC_WAY_SHIFT);
+ int way = FIELD_EX32(env->tlbmisc, CR_TLBMISC, WAY);
int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
- int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
+ int pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID);
int g = FIELD_EX32(v, CR_TLBACC, G);
int valid = FIELD_EX32(vpn, CR_TLBACC, PFN) < 0xC0000;
Nios2TLBEntry *entry =
@@ -117,10 +117,8 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t
v)
entry->data = newData;
}
/* Auto-increment tlbmisc.WAY */
- env->tlbmisc =
- (env->tlbmisc & ~CR_TLBMISC_WAY_MASK) |
- (((way + 1) & (cpu->tlb_num_ways - 1)) <<
- CR_TLBMISC_WAY_SHIFT);
+ env->tlbmisc = FIELD_DP32(env->tlbmisc, CR_TLBMISC, WAY,
+ (way + 1) & (cpu->tlb_num_ways - 1));
}
/* Writes to TLBACC don't change the read-back value */
@@ -130,24 +128,25 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t
v)
void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
{
Nios2CPU *cpu = env_archcpu(env);
+ uint32_t new_pid = FIELD_EX32(v, CR_TLBMISC, PID);
+ uint32_t old_pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID);
+ uint32_t way = FIELD_EX32(v, CR_TLBMISC, WAY);
- trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT,
+ trace_nios2_mmu_write_tlbmisc(way,
(v & CR_TLBMISC_RD) ? 'R' : '.',
(v & CR_TLBMISC_WR) ? 'W' : '.',
(v & CR_TLBMISC_DBL) ? '2' : '.',
(v & CR_TLBMISC_BAD) ? 'B' : '.',
(v & CR_TLBMISC_PERM) ? 'P' : '.',
(v & CR_TLBMISC_D) ? 'D' : '.',
- (v & CR_TLBMISC_PID_MASK) >> 4);
+ new_pid);
- if ((v & CR_TLBMISC_PID_MASK) !=
- (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) {
- mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >>
- CR_TLBMISC_PID_SHIFT);
+ if (new_pid != old_pid) {
+ mmu_flush_pid(env, old_pid);
}
+
/* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */
if (v & CR_TLBMISC_RD) {
- int way = (v >> CR_TLBMISC_WAY_SHIFT);
int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
Nios2TLBEntry *entry =
&env->mmu.tlb[(way * cpu->tlb_num_ways) +
@@ -156,10 +155,8 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t
v)
env->tlbacc &= R_CR_TLBACC_IG_MASK;
env->tlbacc |= entry->data;
env->tlbacc |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0;
- env->tlbmisc =
- (v & ~CR_TLBMISC_PID_MASK) |
- ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) <<
- CR_TLBMISC_PID_SHIFT);
+ env->tlbmisc = FIELD_DP32(v, CR_TLBMISC, PID,
+ entry->tag & ((1 << cpu->pid_num_bits) - 1));
env->pteaddr = FIELD_DP32(env->pteaddr, CR_PTEADDR, VPN,
entry->tag >> TARGET_PAGE_BITS);
} else {
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 3cdef16519..77b3bf05f3 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -910,7 +910,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n",
env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK,
- (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4,
+ FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID),
env->mmu.tlbacc_wr);
#endif
qemu_fprintf(f, "\n\n");
--
2.25.1
- Re: [PATCH v4 14/33] target/nios2: Use hw/registerfields.h for CR_TLBACC fields, (continued)
- [PATCH v4 26/33] target/nios2: Update helper_eret for shadow registers, Richard Henderson, 2022/03/08
- [PATCH v4 22/33] target/nios2: Introduce dest_gpr, Richard Henderson, 2022/03/08
- [PATCH v4 18/33] target/nios2: Implement cpuid, Richard Henderson, 2022/03/08
- [PATCH v4 27/33] target/nios2: Create EXCP_SEMIHOST for semi-hosting, Richard Henderson, 2022/03/08
- [PATCH v4 29/33] target/nios2: Implement EIC interrupt processing, Richard Henderson, 2022/03/08
- [PATCH v4 15/33] target/nios2: Use hw/registerfields.h for CR_TLBMISC fields,
Richard Henderson <=
- [PATCH v4 31/33] hw/nios2: Introduce Nios2MachineState, Richard Henderson, 2022/03/08
- [PATCH v4 30/33] hw/intc: Vectored Interrupt Controller (VIC), Richard Henderson, 2022/03/08
- [PATCH v4 32/33] hw/nios2: Move memory regions into Nios2Machine, Richard Henderson, 2022/03/08