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[PULL 17/22] x86: Add AMX CPUIDs enumeration
From: |
Paolo Bonzini |
Subject: |
[PULL 17/22] x86: Add AMX CPUIDs enumeration |
Date: |
Tue, 8 Mar 2022 12:34:40 +0100 |
From: Jing Liu <jing2.liu@intel.com>
Add AMX primary feature bits XFD and AMX_TILE to
enumerate the CPU's AMX capability. Meanwhile, add
AMX TILE and TMUL CPUID leaf and subleaves which
exist when AMX TILE is present to provide the maximum
capability of TILE and TMUL.
Signed-off-by: Jing Liu <jing2.liu@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-6-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 55 ++++++++++++++++++++++++++++++++++++++++---
target/i386/kvm/kvm.c | 4 +++-
2 files changed, 55 insertions(+), 4 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 79e24bb23f..351a1e4f2a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -575,6 +575,18 @@ static CPUCacheInfo legacy_l3_cache = {
#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support
2K,4K,8K,16K,32K,64K */
+/* CPUID Leaf 0x1D constants: */
+#define INTEL_AMX_TILE_MAX_SUBLEAF 0x1
+#define INTEL_AMX_TOTAL_TILE_BYTES 0x2000
+#define INTEL_AMX_BYTES_PER_TILE 0x400
+#define INTEL_AMX_BYTES_PER_ROW 0x40
+#define INTEL_AMX_TILE_MAX_NAMES 0x8
+#define INTEL_AMX_TILE_MAX_ROWS 0x10
+
+/* CPUID Leaf 0x1E constants: */
+#define INTEL_AMX_TMUL_MAX_K 0x10
+#define INTEL_AMX_TMUL_MAX_N 0x40
+
void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
uint32_t vendor2, uint32_t vendor3)
{
@@ -844,8 +856,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"avx512-vp2intersect", NULL, "md-clear", NULL,
NULL, NULL, "serialize", NULL,
"tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
- NULL, NULL, NULL, "avx512-fp16",
- NULL, NULL, "spec-ctrl", "stibp",
+ NULL, NULL, "amx-bf16", "avx512-fp16",
+ "amx-tile", "amx-int8", "spec-ctrl", "stibp",
NULL, "arch-capabilities", "core-capability", "ssbd",
},
.cpuid = {
@@ -910,7 +922,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
"xsaveopt", "xsavec", "xgetbv1", "xsaves",
- NULL, NULL, NULL, NULL,
+ "xfd", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
@@ -5586,6 +5598,43 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
}
break;
}
+ case 0x1D: {
+ /* AMX TILE */
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) {
+ break;
+ }
+
+ if (count == 0) {
+ /* Highest numbered palette subleaf */
+ *eax = INTEL_AMX_TILE_MAX_SUBLEAF;
+ } else if (count == 1) {
+ *eax = INTEL_AMX_TOTAL_TILE_BYTES |
+ (INTEL_AMX_BYTES_PER_TILE << 16);
+ *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16);
+ *ecx = INTEL_AMX_TILE_MAX_ROWS;
+ }
+ break;
+ }
+ case 0x1E: {
+ /* AMX TMUL */
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) {
+ break;
+ }
+
+ if (count == 0) {
+ /* Highest numbered palette subleaf */
+ *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8);
+ }
+ break;
+ }
case 0x40000000:
/*
* CPUID code in kvm_arch_init_vcpu() ignores stuff
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 1e4436ee74..385c5f8ed3 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -1780,7 +1780,9 @@ int kvm_arch_init_vcpu(CPUState *cs)
c = &cpuid_data.entries[cpuid_i++];
}
break;
- case 0x14: {
+ case 0x14:
+ case 0x1d:
+ case 0x1e: {
uint32_t times;
c->function = i;
--
2.35.1
- [PULL v2 00/22] QEMU changes for 7.0 soft freeze, Paolo Bonzini, 2022/03/08
- [PULL 01/22] whpx: Fixed reporting of the CPU context to GDB for 64-bit, Paolo Bonzini, 2022/03/08
- [PULL 02/22] whpx: Fixed incorrect CR8/TPR synchronization, Paolo Bonzini, 2022/03/08
- [PULL 04/22] meson: fix generic location of vss headers, Paolo Bonzini, 2022/03/08
- [PULL 03/22] vmxcap: Add 5-level EPT bit, Paolo Bonzini, 2022/03/08
- [PULL 06/22] qga/vss: update informative message about MinGW, Paolo Bonzini, 2022/03/08
- [PULL 05/22] qga/vss-win32: check old VSS SDK headers, Paolo Bonzini, 2022/03/08
- [PULL 14/22] x86: Add AMX XTILECFG and XTILEDATA components, Paolo Bonzini, 2022/03/08
- [PULL 17/22] x86: Add AMX CPUIDs enumeration,
Paolo Bonzini <=
- [PULL 12/22] linux-headers: include missing changes from 5.17, Paolo Bonzini, 2022/03/08
- [PULL 07/22] update meson-buildoptions.sh, Paolo Bonzini, 2022/03/08
- [PULL 08/22] kvm-irqchip: introduce new API to support route change, Paolo Bonzini, 2022/03/08
- [PULL 10/22] target/i386: only include bits in pg_mode if they are not ignored, Paolo Bonzini, 2022/03/08
- [PULL 09/22] kvm/msi: do explicit commit when adding msi routes, Paolo Bonzini, 2022/03/08
- [PULL 13/22] x86: Fix the 64-byte boundary enumeration for extended state, Paolo Bonzini, 2022/03/08
- [PULL 16/22] x86: Add XFD faulting bit for state components, Paolo Bonzini, 2022/03/08
- [PULL 18/22] x86: add support for KVM_CAP_XSAVE2 and AMX state migration, Paolo Bonzini, 2022/03/08
- [PULL 20/22] i386: Add Icelake-Server-v6 CPU model with 5-level EPT support, Paolo Bonzini, 2022/03/08
- [PULL 15/22] x86: Grant AMX permission for guest, Paolo Bonzini, 2022/03/08