[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v4 4/7] target/riscv: cpu: Add a config option for native debug
From: |
Bin Meng |
Subject: |
[PATCH v4 4/7] target/riscv: cpu: Add a config option for native debug |
Date: |
Tue, 15 Mar 2022 14:55:26 +0800 |
From: Bin Meng <bin.meng@windriver.com>
Add a config option to enable support for native M-mode debug.
This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v2)
Changes in v2:
- change the config option to 'disabled' by default
target/riscv/cpu.h | 4 +++-
target/riscv/cpu.c | 5 +++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ad35129239..d3e884452b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -79,7 +79,8 @@ enum {
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
RISCV_FEATURE_MISA,
- RISCV_FEATURE_AIA
+ RISCV_FEATURE_AIA,
+ RISCV_FEATURE_DEBUG
};
#define PRIV_VERSION_1_10_0 0x00011000
@@ -388,6 +389,7 @@ struct RISCVCPUConfig {
bool pmp;
bool epmp;
bool aia;
+ bool debug;
uint64_t resetvec;
};
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6a4c94da2a..eb2be5fa05 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -541,6 +541,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
riscv_set_feature(env, RISCV_FEATURE_AIA);
}
+ if (cpu->cfg.debug) {
+ riscv_set_feature(env, RISCV_FEATURE_DEBUG);
+ }
+
set_resetvec(env, cpu->cfg.resetvec);
/* Validate that MISA_MXL is set properly. */
@@ -780,6 +784,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+ DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
--
2.25.1
- [PATCH v4 0/7] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs, Bin Meng, 2022/03/15
- [PATCH v4 1/7] target/riscv: Add initial support for the Sdtrig extension, Bin Meng, 2022/03/15
- [PATCH v4 2/7] target/riscv: machine: Add debug state description, Bin Meng, 2022/03/15
- [PATCH v4 3/7] target/riscv: debug: Implement debug related TCGCPUOps, Bin Meng, 2022/03/15
- [PATCH v4 4/7] target/riscv: cpu: Add a config option for native debug,
Bin Meng <=
- [PATCH v4 5/7] target/riscv: csr: Hook debug CSR read/write, Bin Meng, 2022/03/15
- [PATCH v4 6/7] target/riscv: cpu: Enable native debug feature, Bin Meng, 2022/03/15
- [PATCH v4 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint(), Bin Meng, 2022/03/15
- Re: [PATCH v4 0/7] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs, Alistair Francis, 2022/03/18