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Re: [PATCH v4 6/7] target/riscv: cpu: Enable native debug feature
From: |
Alistair Francis |
Subject: |
Re: [PATCH v4 6/7] target/riscv: cpu: Enable native debug feature |
Date: |
Fri, 18 Mar 2022 12:17:14 +1000 |
On Tue, Mar 15, 2022 at 5:02 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Turn on native debug feature by default for all CPUs.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - enable debug feature by default for all CPUs
>
> target/riscv/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ba9cc3bcd6..08266b163d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -788,7 +788,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> - DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false),
> + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
>
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> --
> 2.25.1
>
>
- [PATCH v4 0/7] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs, Bin Meng, 2022/03/15
- [PATCH v4 1/7] target/riscv: Add initial support for the Sdtrig extension, Bin Meng, 2022/03/15
- [PATCH v4 2/7] target/riscv: machine: Add debug state description, Bin Meng, 2022/03/15
- [PATCH v4 3/7] target/riscv: debug: Implement debug related TCGCPUOps, Bin Meng, 2022/03/15
- [PATCH v4 4/7] target/riscv: cpu: Add a config option for native debug, Bin Meng, 2022/03/15
- [PATCH v4 5/7] target/riscv: csr: Hook debug CSR read/write, Bin Meng, 2022/03/15
- [PATCH v4 6/7] target/riscv: cpu: Enable native debug feature, Bin Meng, 2022/03/15
- Re: [PATCH v4 6/7] target/riscv: cpu: Enable native debug feature,
Alistair Francis <=
- [PATCH v4 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint(), Bin Meng, 2022/03/15
- Re: [PATCH v4 0/7] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs, Alistair Francis, 2022/03/18