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[PATCH v3 2/6] target/arm: Make rvbar settable after realize
From: |
Edgar E. Iglesias |
Subject: |
[PATCH v3 2/6] target/arm: Make rvbar settable after realize |
Date: |
Wed, 16 Mar 2022 17:46:41 +0100 |
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Make the rvbar property settable after realize. This is done
in preparation to model the ZynqMP's runtime configurable rvbar.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/arm/cpu.h | 3 ++-
target/arm/cpu.c | 12 +++++++-----
target/arm/helper.c | 10 +++++++---
3 files changed, 16 insertions(+), 9 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 157f214cce..23879de5fa 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -447,6 +447,7 @@ typedef struct CPUArchState {
uint64_t vbar_el[4];
};
uint32_t mvbar; /* (monitor) vector base address register */
+ uint64_t rvbar; /* rvbar sampled from rvbar property at reset */
struct { /* FCSE PID. */
uint32_t fcseidr_ns;
uint32_t fcseidr_s;
@@ -985,7 +986,7 @@ struct ArchCPU {
/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
uint32_t dcz_blocksize;
- uint64_t rvbar;
+ uint64_t rvbar_prop; /* Property/input signals. */
/* Configurable aspects of GIC cpu interface (which is part of the CPU) */
int gic_num_lrs; /* number of list registers */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 185d4e774d..cd2c1fc7da 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -235,7 +235,10 @@ static void arm_cpu_reset(DeviceState *dev)
} else {
env->pstate = PSTATE_MODE_EL1h;
}
- env->pc = cpu->rvbar;
+
+ /* Sample rvbar at reset. */
+ env->cp15.rvbar = cpu->rvbar_prop;
+ env->pc = env->cp15.rvbar;
#endif
} else {
#if defined(CONFIG_USER_ONLY)
@@ -1130,9 +1133,6 @@ static Property arm_cpu_reset_cbar_property =
static Property arm_cpu_reset_hivecs_property =
DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
-static Property arm_cpu_rvbar_property =
- DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
-
#ifndef CONFIG_USER_ONLY
static Property arm_cpu_has_el2_property =
DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
@@ -1235,7 +1235,9 @@ void arm_cpu_post_init(Object *obj)
}
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
- qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property);
+ object_property_add_uint64_ptr(obj, "rvbar",
+ &cpu->rvbar_prop,
+ OBJ_PROP_FLAG_READWRITE);
}
#ifndef CONFIG_USER_ONLY
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 088956eecf..210db501f1 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7967,7 +7967,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
ARMCPRegInfo rvbar = {
.name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
- .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
+ .access = PL1_R,
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
};
define_one_arm_cp_reg(cpu, &rvbar);
}
@@ -8011,7 +8012,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
ARMCPRegInfo rvbar = {
.name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
- .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
+ .access = PL2_R,
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
};
define_one_arm_cp_reg(cpu, &rvbar);
}
@@ -8048,7 +8050,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
ARMCPRegInfo el3_regs[] = {
{ .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
- .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar
},
+ .access = PL3_R,
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+ },
{ .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
.access = PL3_RW,
--
2.25.1
- [PATCH v3 0/6] hw/arm: zynqmp: Add CRF and APU control to support PSCI, Edgar E. Iglesias, 2022/03/16
- [PATCH v3 1/6] hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area, Edgar E. Iglesias, 2022/03/16
- [PATCH v3 2/6] target/arm: Make rvbar settable after realize,
Edgar E. Iglesias <=
- [PATCH v3 3/6] hw/misc: Add a model of the Xilinx ZynqMP CRF, Edgar E. Iglesias, 2022/03/16
- [PATCH v3 4/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF, Edgar E. Iglesias, 2022/03/16
- [PATCH v3 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control, Edgar E. Iglesias, 2022/03/16
- [PATCH v3 6/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control, Edgar E. Iglesias, 2022/03/16
- Re: [PATCH v3 0/6] hw/arm: zynqmp: Add CRF and APU control to support PSCI, Peter Maydell, 2022/03/17